Abstract
This paper addresses how formal verification can be applied to find a bottleneck in a gigabit network interface card that prevents the card from achieving the best possible performance. Finding a bottleneck in a gigabit network interface card is not an easy task because it is equipped with sophisticated hardware components, such as multiple DMA engines and separate CPU and memory. Therefore, the interactions between a network interface card and the host are very complex so that the firmware to manage the interactions is also complicated, which makes the bottleneck analysis very difficult. As an alternative approach of the bottleneck analysis, we specify the firmware in a gigabit network interface card and analyze the behavior of the specification with SPIN. As an example of gigabit network interface cards, Myrinet is used in this paper. We show that SPIN can easily verify whether the Myrinet firmware has a bottleneck once the state transitions inside the firmware are modeled properly.
This research was supported in part by the University Software Research Center Supporting Project of the Korea Ministry Information & Communication and by the Korea Science & Engineering Foundation under grant No. R01-2000-00287.
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Jin, HW., Bang, KS., Yoo, C., Choi, JY., Cha, Hj. (2002). Bottleneck Analysis of a Gigabit Network Interface Card: Formal Verification Approach. In: Bošnački, D., Leue, S. (eds) Model Checking Software. SPIN 2002. Lecture Notes in Computer Science, vol 2318. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46017-9_13
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DOI: https://doi.org/10.1007/3-540-46017-9_13
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