Abstract
The subgraph isomorphism problem has various important applications, although it is generally NP-complete and dificult to solve. This paper examines the feasibility of a data dependent circuit for the subgraph isomorphism problem, which is particularly suitable for FPGA implementation. For graphs of 32 vertices, the average logic scale of data dependent circuits is only 5% of the corresponding data independent circuit. The circuit is estimated to be 460 times faster than the software for 32 vertices. Even if the circuit generation time is included, a data dependent circuit is expected to be two times faster than software when there are 32 vertices. For larger graphs, the performance gain would be far larger.
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© 2002 Springer-Verlag Berlin Heidelberg
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Ichikawa, S., Yamamoto, S. (2002). Data Dependent Circuit for Subgraph Isomorphism Problem. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_109
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DOI: https://doi.org/10.1007/3-540-46117-5_109
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