Abstract
In this paper, we propose an algorithm of placement and routing for FPGA accelerators. The algorithm is designed to reduce the time for placement and routing of the register transfer level codes generated by a C to HDL compiler. In the codes generated from algorithms written in programming languages, only the limited kinds of operations are used, and they have strong sequentiality from top to bottom. Therefore, in our approach, all circuits for operations in the codes are placed and routed sequentially from top to bottom without finding global optimal placement in order to reduce the computation time. Experiments on some circuits showed good results. The execution time for placement/ routing of about 100K gate circuits is a few seconds and more than 70% of CLBs can be utilized.
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References
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© 2002 Springer-Verlag Berlin Heidelberg
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Miyashita, A., Fujiwara, T., Maruyama, T. (2002). A Placement/Routing Approach for FPGA Accelerators. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_135
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DOI: https://doi.org/10.1007/3-540-46117-5_135
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