Abstract
Field Programmable Gate Arrays (FPGAs) can be used to implement partial run-time reconfigurable (RTR) systems. A tool called PARBIT has been developed that transforms FPGA configuration bitstreams into partial bitstreams. With this tool it is possible to define a partial reconfigurable area inside the FPGA and download it into a specified region of the FPGA device. This paper presents PARBIT, the methodology used to design the partial RTR system, and three application examples.
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Horta, E.L., Lockwood, J.W., Kofuji, S.T. (2002). Using PARBIT to Implement Partial Run-Time Reconfigurable Systems. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_20
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DOI: https://doi.org/10.1007/3-540-46117-5_20
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