Abstract
This work explores the effect of adding a new partitioning step into the traditional complex programmable logic device (CPLD) CAD flow. A novel algorithm based on Rent’s rule and simulated annealing partitions a design before it enters the place and route stage in CPLD CAD. The resulting partitions are then placed using an enhanced placement tool. Experiments conducted on Altera’a APEX20K chips indicate that a partitioned placement can provide an average performance gain of 7% over flat placements.
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References
Altera. “LogicLock Methodology White Paper”. Available at: http://www.altera.com/literature/wp/wp logiclock.pdf.
Altera. Altera 2000 Databook. Available at: http://www.altera.com/html/literature/lds.html.
D. P. Singh, T. P. Borer and S. D. Brown. “Constrained FPGA Placement Algorithms for Timing Optimization”. ACM Intl. Conf. FPGAs, submitted, 2003.
C. J. Alpert and A. B. Kahng. “Recent Directions in Netlist Partitioning: A Survey”. Integration: The VLSI Journal, 19:1–81, 1995.
K. Roy and C. Sechen. “A Timing-Driven n-way Chip and Multi-Chip Partitioner”. In Proc. IEEE/ACM Intl. Conf. Computer-Aided Design, pages 240–247, 1993.
W. Sun and C. Sechen. “Efficient and Effective Placement for Very Large Circuits”. In Proc. IEEE/ACM Intl. Conf. Computer-Aided Design, pages 170–177, 1993.
D. M. Schuler and E. G. Ulrich. “Clustering and Linear Placement”. In Proc. IEEE/ACM Design Automation Conf., pages 50–56, 1972.
H. Shin and C. Kim. “A Simple Yet Effective Technique for Partitioning”. IEEE Trans. VLSI Systems, 1(3): 380–386, September 1993.
T.-K. Ng, J. Oldfield and V. Pitchumani. “Improvements of a Mincut Partition Algorithm”. In Proc. IEEE/ACM Intl. Conf. Computer-Aided Design, pages 470–473, 1987.
L. Hagen, A. B. Kahng, F. J. Kurdahi and C. Ramachandran. “On the Intrinsic Rent Parameter and Spectra-Based Partitioning Methodologies”. IEEE Trans. Computer-Aided Design, 13(1):27–37, 1994.
A. Singh, G. Parthasarathy and M. Marek-Sadowska. “Interconnect Resource-Aware Placement for Hierarchical FPGAs”. In Proc. IEEE/ACM Intl. Conf. Computer-Aided Design, pages 132–136, 2001.
J. Dambre, P. Verplaetse, D. Stroobandt and J. Van Campenhout. “On Rent’s Rule for Rectangular Regions”. In Proc. IEEE/ACM Intl. Workshop on System-Level Interconnect Prediction, pages 49–56, 2001.
X. Yang, R. Kastner and M. Sarrafzadeh. “Congestion Estimation During Top-Down Placement”. In Proc. Intl. Symp. on Physical Design, pages 164–169, 2001.
D. Stroobandt. “A Priori System-Level Interconnect Prediction: Rent’s Rule and Wire Length Distribution Models”. In Proc. IEEE/ACM Intl. Workshop on System-Level Interconnect Prediction, pages 3–21, 2001.
R. B. Hitchcock, G. L. Smith and D. D. Cheng. “Timing Analysis of Computer Hardware”. IBM Journal of Research and Development, 26(1):100–105, January 1982.
B. Landman and R. Russo. “On a Pin Versus Block Relationship for Partitions of Logic Graphs”. IEEE Transactions on Computers, c-20:1469–1479, 1971.
S. Kirkpatrick, C.D. Gelatt and M.P. Vecchi. “Optimization by Simulated Annealing”. Science, 220:671–680, 1983.
V. Betz, J. Rose and A. Marquardt. “Architecture and CAD for Deep-Submicron FPGAs”. Kluwer Academic Publishers, 1999.
M. Huang, F. Romeo and A. Sangiovanni-Vincentelli. “An Efficient General Cooling Schedule for Simulated Annealing”. In Proc. IEEE/ACM Intl. Conf. Computer-Aided Design, pages 381–384, 1986.
J. Lam and J.-M. Delosme. “Performance of a New Annealing Schedule”. In Proc. IEEE/ACM Intl. Design Automation Conf., pages 306–311, 1988.
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Manohararajah, V., Borer, T., Brown, S.D., Vranesic, Z. (2002). Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_25
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DOI: https://doi.org/10.1007/3-540-46117-5_25
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