Skip to main content

Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices

  • Conference paper
  • First Online:
Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream (FPL 2002)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2438))

Included in the following conference series:

Abstract

This work explores the effect of adding a new partitioning step into the traditional complex programmable logic device (CPLD) CAD flow. A novel algorithm based on Rent’s rule and simulated annealing partitions a design before it enters the place and route stage in CPLD CAD. The resulting partitions are then placed using an enhanced placement tool. Experiments conducted on Altera’a APEX20K chips indicate that a partitioned placement can provide an average performance gain of 7% over flat placements.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Altera. “LogicLock Methodology White Paper”. Available at: http://www.altera.com/literature/wp/wp logiclock.pdf.

  2. Altera. Altera 2000 Databook. Available at: http://www.altera.com/html/literature/lds.html.

  3. D. P. Singh, T. P. Borer and S. D. Brown. “Constrained FPGA Placement Algorithms for Timing Optimization”. ACM Intl. Conf. FPGAs, submitted, 2003.

    Google Scholar 

  4. C. J. Alpert and A. B. Kahng. “Recent Directions in Netlist Partitioning: A Survey”. Integration: The VLSI Journal, 19:1–81, 1995.

    Google Scholar 

  5. K. Roy and C. Sechen. “A Timing-Driven n-way Chip and Multi-Chip Partitioner”. In Proc. IEEE/ACM Intl. Conf. Computer-Aided Design, pages 240–247, 1993.

    Google Scholar 

  6. W. Sun and C. Sechen. “Efficient and Effective Placement for Very Large Circuits”. In Proc. IEEE/ACM Intl. Conf. Computer-Aided Design, pages 170–177, 1993.

    Google Scholar 

  7. D. M. Schuler and E. G. Ulrich. “Clustering and Linear Placement”. In Proc. IEEE/ACM Design Automation Conf., pages 50–56, 1972.

    Google Scholar 

  8. H. Shin and C. Kim. “A Simple Yet Effective Technique for Partitioning”. IEEE Trans. VLSI Systems, 1(3): 380–386, September 1993.

    Article  Google Scholar 

  9. T.-K. Ng, J. Oldfield and V. Pitchumani. “Improvements of a Mincut Partition Algorithm”. In Proc. IEEE/ACM Intl. Conf. Computer-Aided Design, pages 470–473, 1987.

    Google Scholar 

  10. L. Hagen, A. B. Kahng, F. J. Kurdahi and C. Ramachandran. “On the Intrinsic Rent Parameter and Spectra-Based Partitioning Methodologies”. IEEE Trans. Computer-Aided Design, 13(1):27–37, 1994.

    Article  Google Scholar 

  11. A. Singh, G. Parthasarathy and M. Marek-Sadowska. “Interconnect Resource-Aware Placement for Hierarchical FPGAs”. In Proc. IEEE/ACM Intl. Conf. Computer-Aided Design, pages 132–136, 2001.

    Google Scholar 

  12. J. Dambre, P. Verplaetse, D. Stroobandt and J. Van Campenhout. “On Rent’s Rule for Rectangular Regions”. In Proc. IEEE/ACM Intl. Workshop on System-Level Interconnect Prediction, pages 49–56, 2001.

    Google Scholar 

  13. X. Yang, R. Kastner and M. Sarrafzadeh. “Congestion Estimation During Top-Down Placement”. In Proc. Intl. Symp. on Physical Design, pages 164–169, 2001.

    Google Scholar 

  14. D. Stroobandt. “A Priori System-Level Interconnect Prediction: Rent’s Rule and Wire Length Distribution Models”. In Proc. IEEE/ACM Intl. Workshop on System-Level Interconnect Prediction, pages 3–21, 2001.

    Google Scholar 

  15. R. B. Hitchcock, G. L. Smith and D. D. Cheng. “Timing Analysis of Computer Hardware”. IBM Journal of Research and Development, 26(1):100–105, January 1982.

    Article  Google Scholar 

  16. B. Landman and R. Russo. “On a Pin Versus Block Relationship for Partitions of Logic Graphs”. IEEE Transactions on Computers, c-20:1469–1479, 1971.

    Article  Google Scholar 

  17. S. Kirkpatrick, C.D. Gelatt and M.P. Vecchi. “Optimization by Simulated Annealing”. Science, 220:671–680, 1983.

    Article  MathSciNet  Google Scholar 

  18. V. Betz, J. Rose and A. Marquardt. “Architecture and CAD for Deep-Submicron FPGAs”. Kluwer Academic Publishers, 1999.

    Google Scholar 

  19. M. Huang, F. Romeo and A. Sangiovanni-Vincentelli. “An Efficient General Cooling Schedule for Simulated Annealing”. In Proc. IEEE/ACM Intl. Conf. Computer-Aided Design, pages 381–384, 1986.

    Google Scholar 

  20. J. Lam and J.-M. Delosme. “Performance of a New Annealing Schedule”. In Proc. IEEE/ACM Intl. Design Automation Conf., pages 306–311, 1988.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2002 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Manohararajah, V., Borer, T., Brown, S.D., Vranesic, Z. (2002). Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_25

Download citation

  • DOI: https://doi.org/10.1007/3-540-46117-5_25

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-44108-3

  • Online ISBN: 978-3-540-46117-3

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics