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Run-Time Adaptive Flexible Instruction Processors

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Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream (FPL 2002)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2438))

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Abstract

This paper explores run-time adaptation of Flexible Instruction Processors (FIPs), a method for parametrising descriptions and development of instruction processors. The run-time adaptability of a FIPsy stem allows it to evolve to suit the requirements of the user, by requesting automatic refinement based on instruction usage patterns. The techniques and tools that we have developed include: (a) a runtime environment that manages the reconfiguration of the FIPs o that it can execute a given application as efficiently as possible; (b) mechanisms to accumulate run-time metrics, and analysis of the metrics to allow the run-time environment to request for automatic refinements; (c) techniques to automatically customise a FIPto an application.

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References

  1. B. Gladman. Implementations of AES (Rijndael) in C/C++ and Assembler. http://fp.gladman.plus.com/cryptography technology/rijndael/.

  2. J. A. Fisher. Customized instruction sets for embedded processors. In Proc. 36th Design Automation Conference, 1999.

    Google Scholar 

  3. H. McGhan and M. O’Connor. PicoJava: a direct execution engine for Java bytecode. IEEE Computer. October 1998.

    Google Scholar 

  4. M. McLoone and J. McCanny. Single-chip FPGA implementation of the Advanced Encryption Standard algorithm. In Proc. FPL, LNCS 2147. Springer, 2001.

    Google Scholar 

  5. N. Weaver and J. Wawrzynek. Very high performance, compact AES implementations in Xilinx FPGAs. http://www.cs.berkeley.edu/~nweaver/sfra/rijndael.pdf.

  6. R. Razdan and M. D. Smith. A high-performance microarchitecture with hardwareprogrammable functional units. In Proc. MICRO-27. 1994.

    Google Scholar 

  7. S. Seng, W. Luk and P. Cheung. Flexible instruction processors. In Proc. CASES. ACM, 2000.

    Google Scholar 

  8. N. Shirazi, W. Luk and P. Cheung. Run-time management of dynamically reconfigurable designs. In Proc. FPL, LNCS 1482. Springer, 1998.

    Google Scholar 

  9. N. Shirazi, W. Luk and P. Cheung. Framework and tools for run-time reconfigurable designs. IEE Proc.-Comput. Digit. Tech., May 2000.

    Google Scholar 

  10. S. Trimberger, D. Carberry and A. Johnson. A time-multiplexed FPGA. In Proc. FCCM. IEEE Computer Society Press, 1997.

    Google Scholar 

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Author information

Authors and Affiliations

  1. Department of Computing, Imperial College, London, UK

    Shay Seng & Wayne Luk

  2. Department of EEE, Imperial College, London, UK

    Peter Y.K. Cheung

Authors
  1. Shay Seng
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  2. Wayne Luk
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  3. Peter Y.K. Cheung
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Editor information

Editors and Affiliations

  1. Institut für Datentechnik, FG Mikroelektronische Systeme, Technische Universität Darmstadt, Karlstraße 15, 64283, Darmstadt, Germany

    Manfred Glesner  & Peter Zipf  & 

  2. Microelectronics Department, LIRMM, 161 rue Ada, 34392, Montpellier Cedex, France

    Michel Renovell

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© 2002 Springer-Verlag Berlin Heidelberg

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Seng, S., Luk, W., Cheung, P.Y. (2002). Run-Time Adaptive Flexible Instruction Processors. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_57

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  • DOI: https://doi.org/10.1007/3-540-46117-5_57

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-44108-3

  • Online ISBN: 978-3-540-46117-3

  • eBook Packages: Springer Book Archive

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