Abstract
We present an implementation of a simplified scalable architecture for the efficient realization of 3-D adaptive LUM smoother in the Field Pro- grammable Logic Devices (FPLDs). The proposed filter architecture takes advantages of a combination of recently provided Boolean LUM smoothers with bit-serial realization of stack filters. In order to decrease hardware requirements, we implemented a highly reduced filter structure that is completely modular, scalable and optimized for hardware implementation in FPLD. Introduced simplifications significantly decrease a circuit complexity, however they still provide excellent smoothing capability and provide real-time performance for processing of 3-D signals with sampling frequencies up to 65 Msamples/second.
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Fischer, V., Drutarovský, M., Lukac, R. (2002). Implementation of 3-D Adaptive LUM Smoother in Reconfigurable Hardware. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_74
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DOI: https://doi.org/10.1007/3-540-46117-5_74
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