Skip to main content

Rijndael Cryptographic Engine on the UltraSONIC Reconfigurable Platform

  • Conference paper
  • First Online:
Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream (FPL 2002)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2438))

Included in the following conference series:

  • 982 Accesses

Abstract

This paper describes a high performance implementation of the Rijndael encryption algorithm using the UltraSONIC reconfigurable platform. We show how the UltraSONIC design methodology allowed us to develop a complete hardware/software solution in a matter of weeks. Reconfiguration is exploited to maximise the use of the available hardware resources. A modular implementation allows the trade off of encryption security against hardware resources. The flexibility of the UltraSONIC architecture allows a single implementation to process data from either the host computer or external real- time video sources. We are able to meet the requirements for processing high definition in real-time, achieving a throughput of 2.1 Gbit/sec. In software acceleration mode we are able to achieve more than 4 times speed up compared with a 1GHz Pentium III system.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Daemen, J., Rijmen, V.: AES Proposal: Rijndael, NIST AES Proposal, 1998.

    Google Scholar 

  2. Weeks, B., Bean, M., Rozylowicz, T., Ficke, C.: Hardware Performance Simulations of Round 2 (Advanced Encryption Standard) Algorithms, The Third Advanced Encryption Standard Candidate Conference, April 13–14, 2000, New York, NY, USA, 286–304

    Google Scholar 

  3. Haynes, S.D., Stone, J., Cheung, P.Y.K, Luk, W.: Video Image Processing with the Sonic Architecture. IEEE Computer, April 2000 50–57

    Google Scholar 

  4. McLoone, M., McCanny, J.V.: Single-Chip FPGA Implementation of the Advanced Encryption Standard (Rijndael), Proc. Of the Field-Programmable Logic and Applications 11th International Conference, FPL 2001, 162–171

    Google Scholar 

  5. Chodowiec, P., Gaj, K., Bellows, P., Schott, B.: Experimental Testing of the Gigabit IPSec. Compliant Implementations of the Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator board. Proc. Information Security Conference, 2001 220–234

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2002 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Moreira, E.A., McAlpine, P.L., Haynes, S.D. (2002). Rijndael Cryptographic Engine on the UltraSONIC Reconfigurable Platform. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_79

Download citation

  • DOI: https://doi.org/10.1007/3-540-46117-5_79

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-44108-3

  • Online ISBN: 978-3-540-46117-3

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics