Abstract
We present an attempt to use the model checker Spin as a verification engine for SDL, with special emphasis put on the verification of timing properties of SDL models. We have extended Spin with a front-end that allows to translate SDL to Promela (the input language of Spin), and a back-end that allows to analyse timing properties. Compared with the previous attempts, our approach allows to verify not only qualitative but also quantitative aspects of SDL timers, and our translation of SDL to Promela handles the SDL timers in a correct way. We applied the toolset to the verification of a substantial part of a complex industrial protocol. This allowed to expose several non-trivial errors in the protocol’s design.
This research has been supported by the VIRES project (Verifying Industrial Reactive Systems, Esprit Long Term Research Project #23498).
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References
R. Alur, D.L. Dill, A Theory of Timed Automata, Theoretical Computer Science, 126, pp.183–235, 1994.
D. Bošnački, D. Dams, Integrating Real Time into Spin: A Prototype Implementation, S. Budkowski, A. Cavalli, E. Najm, editors, Formal Description Techniques and Protocol Specification, Testing and Verification (FORTE/PSTV’98), Kluwer, 1998. 365, 366
M. Bozga, J-C. Fernandez, L. Ghirvu, S. Graf, J.P. Karimm, L. Mounier, J. Sifakis, If: An Intermediate Representation for SDL and its Applications, In Proc. of SDLFORUM’ 99, Montreal, Canada, 1999. 363, 366, 367
I. Dravapoulos, N. Pronios, S. Denazis et al., The Magic WAND, Deliverable 3D2, Wireless ATM MAC, September 1997.
G. J. Holzmann, Design and Validation of Communication Protocols, Prentice Hall, 1991. Also: http://netlib.bell-labs.com/netlib/spin/whatispin.html 363, 365
G.J. Holzmann, J. Patti, Validating SDL Specification: an Experiment, In E. Brinksma, G. Scollo, Ch.A. Vissers, editors, Protocol Specification, Testing and Verification, Enchede, The Netherlands, 6–9 June 1989, pp. 317–326, Amsterdam, 1990. North-Holland. 364, 371
G.J. Holzmann, D. Peled, An Improvement of Formal Verification, PSTV 1994 Conference, Bern, Switzerland, 1994. 366
A. Olsen et al., System Engineering Using SDL-92, Elsevier Science, North-Holland, 1997. 363
D. Peled, Combining Partial Order Reductions with On-the-Fly Model Checking, Computer Aided Verification CAV 94, LCNS 818, pp. 377–390, 1994. 366
H. Tuominen, Embedding a Dialect of SDL in PROMELA, 6th Int. SPIN Workshop, LNCS 1680, pp. 245–260, 1999. 364, 371, 372
Verilog, ObjectGEODE tutorial, Version 1.2, Verilog SA, Toulouse, France, 1996. 364, 366, 369
VIRES, Verifying Industrially Relevant Systems, Esprit Long Term Research Project #23498, http://radon.ics.ele.tue.nl/~vires, 1996. 367
WAND consortium, Magic WAND-Wireless ATM Network Demonstrator, http://www.tik.ee.ethz.ch/~wand, 1996. 364, 373
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Bošnački, D., Dams, D., Holenderski, L., Sidorova, N. (2000). Model Checking SDL with Spin. In: Graf, S., Schwartzbach, M. (eds) Tools and Algorithms for the Construction and Analysis of Systems. TACAS 2000. Lecture Notes in Computer Science, vol 1785. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46419-0_25
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DOI: https://doi.org/10.1007/3-540-46419-0_25
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