Abstract
In this paper, we propose a method to detect and correct design faults in a combinational boolean network, based on the model-based inference. We focus on the design verification for the network with multiple inverter errors. The complexity of this problem is NP-hard and it is harder than the usual verification to find a tractable algorithm. We present an effective algorithm which consists of the generation of the logical formula and its comparison to the specification for each cone in gate implementation. In this algorithm, the heuristic search method is incorporated to avoid the unnecessary backtracking based on the property that a part of the logical formula of each cone must be subformulas of functional specifications if the gate implementation is correct and irredundant.
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Hiratsuka, S., Fusaoka, A. (2002). On a Model-Based Design Verification for Combinatorial Boolean Networks. In: Hendtlass, T., Ali, M. (eds) Developments in Applied Artificial Intelligence. IEA/AIE 2002. Lecture Notes in Computer Science(), vol 2358. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48035-8_73
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DOI: https://doi.org/10.1007/3-540-48035-8_73
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