Skip to main content
SpringerLink
Log in

A Parallel Transitive Closure Computation Algorithm for VLSI Test Generation

  • Conference paper
  • First Online:
Applied Parallel Computing (PARA 2002)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2367))

Included in the following conference series:

Abstract

This paper presents an efficient scalable parallel algorithm for transitive closure computation and its application to solve VLSI test generation problem. The transitive closure computation is the core of the test generation process and it will take huge time, sometimes unaffordable, if it is computed on serial machines for generating patterns for large practical VLSI circuits. The proposed algorithm divides the transitive closure computation into n × n tasks using data parallelism and it takes polylogarithmic time using polynomial number of processors. Load balancing techniques: static and dynamic and performance metrics like speedup, efficiency, scalability and isoefficiency function are taken into account for the algorithm development. The algorithm, so developed, has been implemented in a heterogeneous distributed computing environment using Parallel Virtual Machine (PVM) and successfully tested by generating test patterns for example practical circuits. Experimental results given in the paper show the effectiveness of the proposed algorithm.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. O. H. Ibarra and S. K. Sahni, “Polynomially Complete Fault Detection Problems,” IEEE Trans. on Computers, Vol. C-24, No. 3, pp. 242–249, March 1975.

    Article  MathSciNet  Google Scholar 

  2. V. D. Agrawal and S. C. Seth, Test Generation for VLSI Chips, IEEE Computer Society Press, Los Alamitos, CA, 1988.

    Google Scholar 

  3. P. Goel“An Implicit Enumeration Algorithm to Generate Tests for Combinational Circuits,” IEEE Trans. on Computers, Vol. C-30, No. 3, pp. 215–222, March 1981.

    Google Scholar 

  4. E. H. L. Arts and J. H. Korst, Simulated Annealing and Boltzmann Machines: A Stochastic Approach to Combinatorial Optimization and Neural Computing, Wiley, New York, 1989.

    Google Scholar 

  5. R. H. Klenke, R. D. Williams and J. H. Aylor “Parallel-Processing Techniques for Automatic Test Pattern Generation,” IEEE Computer, Vol. 25, No. 1, pp. 71–84, Jan. 1992.

    Article  Google Scholar 

  6. S. T. Chakradhar, V. D. Agrawal and M. L. Bushnell, “Automatic test generation using quadratic 0-1 programming,” 27th ACM/IEEE Design Automation Conference, 1990, 654–659.

    Google Scholar 

  7. S. T. Chakradhar, M. L. Bushnell, and V. D. Agrawal, “Towards massively parallel automatic test generation,” IEEE Transactions on Computer-Aided Design, Vol. 9, No. 9, Sept. 1990, 2235–2258.

    Article  Google Scholar 

  8. S. T. Chakradhar, V. D. Agrawal, and S. G. Rothweiler, “A transitive closure algorithm for test generation,” IEEE Transactions on Computer-Aided Design, Vol. 12, No. 7, July 1993, 1015–1028.

    Article  Google Scholar 

  9. S.R. Pawagi, P.S. Gopalakrishnan, and I.V. Ramakrishnan, “Computing Dominators in Parallel,” Information Processing Letters, Vol. 24, No. 4, April 1987, 217–221.

    Article  MathSciNet  MATH  Google Scholar 

  10. T. Larrabee, “Test pattern generation using Boolean Satisfiability,” IEEE Transactions on Computer-Aided Design, Vol. 7, Jan. 1992, 4–15.

    Article  Google Scholar 

  11. M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman & Company, San Francisco, 1979.

    MATH  Google Scholar 

  12. D. E. Goldberg, Genetic Algorithms in Search, Optimization and Machine Learning, Addison-Wesley, Reading, Mass., 1989.

    MATH  Google Scholar 

  13. K. A. DeJong and W. M. Spears, “An Analysis of the Interacting Roles of Population Size and Crossover in Genetic Algorithms,” Proc. First Workshop Parallel Problem Solving from Nature, Springer-Verlag, Berlin, 1990, pp. 38–47.

    Google Scholar 

  14. M. Srinivas and L. M. Patnaik, “Adaptive Probabilities of Crossover and Mutation in Genetic Algorithms,” IEEE Trans. on Systems, Man and Cybernetics, Vol. 24, No. 4, July/Aug. 1994, pp. 656–666.

    Article  Google Scholar 

  15. P. Hansen, B. Jaumard, and M. Minoux, ”A Linear Expected-Time Algorithm for Deriving All Logical Conclusions Implied by a Set of Boolean Inequalities” Mathematical Programming, 34(2):223–231, march 1986.

    Google Scholar 

  16. B.F. Wang and G.H. Chen, ”Constant Time Angorithm for the Transitive Closure and Some Related Graph problems on Processor Arrays with Reconfigurable Bus System” IEEE Transactions on Parallel and Distributed Systems, 1(4):500–507, October 1990.

    Google Scholar 

  17. S. Warshall ”A Theorem on Boolean Matrices”, Journal of the ACM, 9(1):11–12, january 1962.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Computer Science & Engineering, TIET, Patiala, 147 004, India

    Seema Bawa

  2. Information Technology Group, IIITM, Gwalior, 474 005, India

    G. K. Sharma

Authors
  1. Seema Bawa
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. G. K. Sharma
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. CSC, P.O. Box 405, 02101, Espoo, Finland

    Juha Fagerholm , Juha Haataja , Jari Järvinen , Mikko Lyly , Peter Råback  & Ville Savolainen , , , ,  & 

Rights and permissions

Reprints and permissions

Copyright information

© 2002 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Bawa, S., Sharma, G.K. (2002). A Parallel Transitive Closure Computation Algorithm for VLSI Test Generation. In: Fagerholm, J., Haataja, J., Järvinen, J., Lyly, M., Råback, P., Savolainen, V. (eds) Applied Parallel Computing. PARA 2002. Lecture Notes in Computer Science, vol 2367. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48051-X_25

Download citation

  • DOI: https://doi.org/10.1007/3-540-48051-X_25

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-43786-4

  • Online ISBN: 978-3-540-48051-8

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation