Skip to main content
SpringerLink
Log in

Implementation of Givens QR-Decomposition in FPGA

  • Conference paper
  • First Online:
Parallel Processing and Applied Mathematics (PPAM 2001)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2328))

Abstract

A new parallel processor structure for Givens QR-decomposition intended for the FPGA implementation is presented. The structure is derived using method of mapping regular algorithms using affine transformations of the algorithm graph. The method supports pipelined processor unit design, and provides efficient hardware utilization. An example of the implementation of this structure in the Xilinx Virtex FPGA devices is presented.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Roelands, W.: Platform FPGA-the Future of Logic Design. XESS Journal. V38, N4 (2000) 4–7

    Google Scholar 

  2. Kung, S.Y.: VLSI processor arrays. Prentice Hall, Englewood Cliffs (1988).

    Google Scholar 

  3. Quinton, P., Robert, Y.: Systolic algorithms and architectures. Prentice Hall, Englewood Cliffs (1991).

    Google Scholar 

  4. Kanevski, J.S., Sergyienko, A.M., Piech, H.: A method for the structural synthesis of pipelined array processors. In: Proc. 1-st Int. Conf. ”Parallel Processing and Applied Mathematics”, PPAM’94, Częstochowa (Poland), Sept. 14–16 (1994) 100–108.

    Google Scholar 

  5. Guzinski, A., Kanevski, J.S., Sergyienko, A.M.: A method for mapping unimodular loops into application-specific parallel architectures.In: Proc. 2-nd Int. Conf. on Parallel Processing and Applied Math.-PPAM’97, Zakopane (Poland) (1997) 362–371.

    Google Scholar 

  6. Kanevski, Ju.S., Wyrzykowski, R., Maslennikov, O.V.: Mapping Recursive Algorithms into Processor Arrays. In: Proc. of the Int. Workshop ”Parallel Numer-ics’94”, Smolenice (1994) 169–191.

    Google Scholar 

  7. Gjotze, J. and Schwiegelsohn. A Square root and division free Givens rotation for solving least square problems on systolic arrays. SIAM J. Sci. Statist. Comput, vol. 12, N4 (1991) 300–807.

    Google Scholar 

  8. Valero-Garcia, M., Navarro, J.J., Llaberia, J.M., Valero, M. and Lang, T.: A method for implementation of one-dimensional systolic algorithms with data contraflow using pipelined functional units. J. of VLSI Signal Processing, vol. 4, (1992) 7–25.

    Article  Google Scholar 

  9. Heller, D.H., Ipsen, I.C.F.: Systolic Networks for Orthogonal Equivalence Transformations and their Application. Conf. on Advanced Research in VLSI. Cambridge. MA; M.I.T. Press (1982) 113–122.

    Google Scholar 

  10. Ahmed, H.M., Desolme, J.M. and Morf, M.: Higly Concurrent computing structures for matrix arithmetic and signal processing. Computer, vol. 15, N1 (1982) 65–82.

    Article  Google Scholar 

  11. A. Bojanczyk, R.P. Brent, H.T. Kung. Numerically stable solution for dense systems of linear equations using mesh-connected processors. SIAM J. Sci. Statist. Comput. V1 (1984) 95–104.

    MathSciNet  Google Scholar 

  12. Gentleman, W.M., Kung, H.T.: Matrix triangularization by systolic arrays. Proc. SPIE, Real-Time Signal Processing IV (1981) 19–26.

    Google Scholar 

  13. Luk, F.T.: A rotation method for computing the QR-decomposition, SIAM J. Sci. Statist. Comput. V7 (1986) 452–459.

    Article  MathSciNet  MATH  Google Scholar 

  14. Schwiegelshohn, V.: One-and two-dimensional arrays for least squares problems. In: Proc. Int. Conf. on Acoust., Speech and Signal Processing, Dallas, T.X. (1987) 791–794.

    Google Scholar 

  15. Chun, J., Kailath, T., Lev-Ari H.: Fast parallel algorithms for QR and triangular factorization. SIAM J. Sci. Statist. Comput. V6 (1987) 899–913.

    MathSciNet  Google Scholar 

  16. Sergyienko, A., Kanevski, J., Maslennikov, O., Wyrzykowski, R.: Mapping Regular Algorithms into Processor Arrays using Program Pipelining. Proc. 1st Int. Conf. on Parallel Computing in Electrical Engineering-PARELEC’98, Bialystok, Sept. 2-5, Poland (1998) 362–371.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Computer Science, National Technical University of Ukraine, Kiev, Ukraine

    Anatoli Sergyienko

  2. Technical University of Koszalin, Koszalin, Poland

    Oleg Maslennikov

Authors
  1. Anatoli Sergyienko
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Oleg Maslennikov
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Institute of Mathematics and Computer Science, Technical University of Czestochowa, Dabrowskiego 73, 42-200, Czestochowa, Poland

    Roman Wyrzykowski

  2. Computer Science Department, University of Tennessee, 122 Volunteer Blvd, Knoxville, TN, 37996-3450, USA

    Jack Dongarra

  3. Computer Science Department, Oklahoma State University, 700 N. Greenwood Ave., Tulsa, OK, 74106, USA

    Marcin Paprzycki

  4. DTU, UNI-C, Danish Computing Centre for Research and Education, Bldg. 304, 2800, Lyngby, Denmark

    Jerzy Waśniewski

Rights and permissions

Reprints and permissions

Copyright information

© 2002 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Sergyienko, A., Maslennikov, O. (2002). Implementation of Givens QR-Decomposition in FPGA. In: Wyrzykowski, R., Dongarra, J., Paprzycki, M., Waśniewski, J. (eds) Parallel Processing and Applied Mathematics. PPAM 2001. Lecture Notes in Computer Science, vol 2328. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48086-2_50

Download citation

  • DOI: https://doi.org/10.1007/3-540-48086-2_50

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-43792-5

  • Online ISBN: 978-3-540-48086-0

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation