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Design of Totally Self-Checking Code-Disjoint Synchronous Sequential Circuits

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Dependable Computing — EDCC-3 (EDCC 1999)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1667))

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Abstract

Several design methods of self-checking synchronous sequential circuits (SMs) have been proposed in the literature. In this paper, we present a new approach to designing totally self-checking (TSC) code-disjoint (CD) SMs protected against errors using unordered codes. It is assumed that D flip-flops are used as the memory elements and that the circuit should be TSC for all single stuck-at faults (except for the faults on the clock lines), and CD for all input unidirectional errors. The initial 2-level AND-OR equations (with all products shared) are checked for self-testing by verifying some algebraic conditions. All stuck-at-1 faults which cannot be detected during normal functioning are identified. Then, the circuit is modified to the AND-AND-OR circuit with generally higher fault coverage. The resulting circuit is minimized using the well known SIS CAD tools. The whole design process has been automated by using the newely developed software tools that accept the BLIF representation of a SM and are compatible with the SIS tools. Many benchmark SMs can now be implemented as TSC with 100% fault coverage.

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Authors and Affiliations

  1. Wroclaw University of Technology Institute of Engineering Cybernetics, 50-370, Wroclaw, Poland

    Jerzy W. Greblicki & Stanisław J. Piestrak

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  1. Jerzy W. Greblicki
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  2. Stanisław J. Piestrak
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Editors and Affiliations

  1. Department of Computer Science and Engineering, Czech Technical University in Prague, Karlovo nam 13, CZ-12135, Prague 2, Czech Republic

    Jan Hlavička

  2. Institut für Technische Informatik, Medizinische Universität zu Lübeck, Ratzeburger Allee 160, 23538, Lübeck, Germany

    Erik Maehle

  3. Department of Measurement and Information Systems, Technical University of Budapest, Pázmány P. sétány 1/d, H-1521, Budapest, Hungary

    András Pataricza

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© 1999 Springer-Verlag Berlin Heidelberg

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Greblicki, J.W., Piestrak, S.J. (1999). Design of Totally Self-Checking Code-Disjoint Synchronous Sequential Circuits. In: Hlavička, J., Maehle, E., Pataricza, A. (eds) Dependable Computing — EDCC-3. EDCC 1999. Lecture Notes in Computer Science, vol 1667. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48254-7_18

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  • DOI: https://doi.org/10.1007/3-540-48254-7_18

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-66483-3

  • Online ISBN: 978-3-540-48254-3

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