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The Speedup Performance of an Associative Memory Based Logic Simulator

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Parallel Computing Technologies (PaCT 1999)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1662))

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Abstract

As circuits increase in size and complexity, there is an ever demanding requirement to accelerate the processing speed of logic simu- lation. Parallel processing has been perceived as an obvious candidate to assist in this goal and numerous parallel processing systems have been investigated. Unfortunately, large speedup figures have eluded these ap- proaches. A large communication overhead due to basic passing of values between processors, elaborate measures to avoid or recover from dead- lock and load balancing techniques, is the principal barrier to achieving high speedup. This paper presents an Associative memory architecture which is the basis of a machine APPLES(Associative Parallel Processor for Logic Event Simulation), specifically designed for parallel discrete event logic simulation. A scan mechanism replaces inter-process commu- nication. This mechanism is well disposed to parallelisation. The machine has been evaluated theoretically and empirically.

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© 1999 Springer-Verlag Berlin Heidelberg

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Dalton, D. (1999). The Speedup Performance of an Associative Memory Based Logic Simulator. In: Malyshkin, V. (eds) Parallel Computing Technologies. PaCT 1999. Lecture Notes in Computer Science, vol 1662. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48387-X_22

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  • DOI: https://doi.org/10.1007/3-540-48387-X_22

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-66363-8

  • Online ISBN: 978-3-540-48387-8

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