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RSA Acceleration with Field Programmable Gate Arrays

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Information Security and Privacy (ACISP 1999)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1587))

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Abstract

An effcient implementations of modular exponentiation, i.e., the main building block in the RSA cryptographic scheme, is achieved by first designing a bit-level systolic array such that the whole procedure of modular exponentiation can be carried out entirely by a single unit without using global interconnections or memory to store intermediate results, and then mapping this design onto Xilinx XC6000 Field Programmable Gate Array.

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© 1999 Springer-Verlag Berlin Heidelberg

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Tiountchik, A., Trichina, E. (1999). RSA Acceleration with Field Programmable Gate Arrays. In: Pieprzyk, J., Safavi-Naini, R., Seberry, J. (eds) Information Security and Privacy. ACISP 1999. Lecture Notes in Computer Science, vol 1587. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48970-3_14

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  • DOI: https://doi.org/10.1007/3-540-48970-3_14

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-65756-9

  • Online ISBN: 978-3-540-48970-2

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