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Algebraic Models of Superscalar Microprocessor Implementations: a Case Study

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Prospects for Hardware Foundations

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1546))

Abstract

We extend a set of algebraic tools for representing microprocessors to model superscalar microprocessor implementations, and apply them to a case study. We develop existing correctness models to accommodate the more advanced timing relationships of superscalar processors, and consider formal verification. We illustrate our tools and techniques with an in-depth treatment of an example superscalar implementation. We use clocks to divide time into (not necessarily equal) segments, defined by the natural timing of the computational process of a device. We formally relate clocks by surjective, monotonic maps called retimings. In the case of superscalar microprocessors, the normal relationship between ‘architectural time’ and ‘implementation time’ is complicated by the fact that events that are distinct in time at the architectural level can occur simultaneously at the implementation level

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Authors and Affiliations

  1. Computer Science, University of Wales, Swansea, Swansea SA2 8PP, UK

    A. C. J. Fox & N. A. Harman

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  1. A. C. J. Fox
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  2. N. A. Harman
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Editors and Affiliations

  1. Department of Computer Science, University of Augsburg, Universitätsstr. 14, D-86135, Augsburg, Germany

    Bernhard Möller

  2. Department of Computer Science, University of Wales at Swansea, Singleton Park, Swansea, SA2 8PP, Wales, UK

    John V. Tucker

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Fox, A.C.J., Harman, N.A. (1998). Algebraic Models of Superscalar Microprocessor Implementations: a Case Study. In: Möller, B., Tucker, J.V. (eds) Prospects for Hardware Foundations. Lecture Notes in Computer Science, vol 1546. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-49254-2_5

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  • DOI: https://doi.org/10.1007/3-540-49254-2_5

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