Abstract
This paper is concerned with efficient hardware architectures for normal basis multipliers in GF(2n). New serial input/parallel output architectures are derived. The complexity of these multipliers is equivalent to the complexity of the Massey-Omura multiplier. We also combine dual basis and normal basis techniques. The duality of normal bases is shown to be equivalent to the symmetry of the logic array of the serial input/parallel output architectures proposed in this paper.
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© 1989 Springer-Verlag Berlin Heidelberg
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Geiselmann, W., Gollmann, D. (1989). Symmetry and duality in normal basis multiplication. In: Mora, T. (eds) Applied Algebra, Algebraic Algorithms and Error-Correcting Codes. AAECC 1988. Lecture Notes in Computer Science, vol 357. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-51083-4_62
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DOI: https://doi.org/10.1007/3-540-51083-4_62
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Online ISBN: 978-3-540-46152-4
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