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Towards systolizing compilation: An overview

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PARLE '89 Parallel Architectures and Languages Europe (PARLE 1989)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 366))

Abstract

A scheme for the compilation of imperative or functional programs into systolic programs is demonstrated on matrix composition and decomposition. Using this scheme, programs for the processor network Warp and for several Transputer networks have been generated. The compilation scheme applies to systolic arrays with straight, constant-speed data streams.

This research was supported in part by the following funding agencies: through Carnegie-Mellon University by the Defense Advanced Research Projects Agency monitored by the Space and Naval Warfare Systems Command under Contract N00039-87-C-0251 and by the Office of Naval Research under Contracts N00014-87-K-0385 and N00014-87-K-0533; through Oxford University by the Science and Engineering Research Council under Contract GR/E 63902; through the University of Texas at Austin by the Office of Naval Research under Contracts N00014-86-K-0763, and by the National Science Foundation under Contract DCR-8610427.

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13 References

  1. Ametek Computer Research Division, “Series 2010 System, General Description”, Issue 3, Ametek, Inc., Apr. 1988.

    Google Scholar 

  2. M. C. Chen, “A Parallel Language and Its Compilation to Multiprocessor Machines”, J. Parallel and Distributed Computing 3, 4 (Dec. 1986), 461–491.

    Google Scholar 

  3. M. C. Chen, “Placement and Interconnection of Systolic Processing Elements: A New LU-Decomposition Algorithm”, Research Report YALEU/DCS/RR-498, Department of Computer Science, Yale University, Oct. 1986.

    Google Scholar 

  4. B. R. Engstrom and P. R. Cappello, “The SDEF Systolic Programming System”, Proc. 1987 Int. Conf. on Parallel Processing, S. Sahni (ed.), The Pennsylvania State University Press, 1987, 645–652; full paper: TRCS87-15, Department of Computer Science, UC Santa Barbara, Aug. 1987; to appear in J. Parallel and Distributed Computing (Aug. 1989).

    Google Scholar 

  5. T. Gross, M. Lam and J. Reinders, “Programming Warp in W2”, Department of Computer Science, Carnegie-Mellon University.

    Google Scholar 

  6. C. A. R. Hoare, “Communicating Sequential Processes” Comm. ACM 21, 8 (Aug. 1978), 666–677.

    Google Scholar 

  7. C.-H. Huang, “The Mechanically Certified Derivation of Concurrency and its Application to Systolic Design”, Ph. D. Thesis, Department of Computer Sciences, The University of Texas at Austin, Aug. 1987.

    Google Scholar 

  8. C.-H. Huang and C. Lengauer, “The Derivation of Systolic Implementations of Programs”, Acta Informatica 24, 6 (Nov. 1987), 595–632.

    Google Scholar 

  9. C.-H. Huang and C. Lengauer, “Mechanically Derived Systolic Solutions to the Algebraic Path Problem”, in VLSI and Computers (CompEuro 87), W. E. Proebster and H. Reiner (eds.), IEEE Computer Society Press, 1987, 307–310; full paper: TR-86-28, Department of Computer Sciences, The University of Texas at Austin, Dec. 1986.

    Google Scholar 

  10. D. G. Hudson and C. Lengauer, “A Systolic Program for Gauss-Jordan Elimination”, Tech. Report, Department of Computer Sciences, The University of Texas at Austin, in preparation.

    Google Scholar 

  11. INMOS, Ltd., occam Programming Manual, Prentice/Hall Int., Series in Computer Science, 1984.

    Google Scholar 

  12. INMOS, Ltd., Transputer Reference Manual, Prentice Hall, 1988.

    Google Scholar 

  13. H. T. Kung and C. E. Leiserson, “Algorithms for VLSI Processor Arrays”, in Introduction to VLSI Systems, C. Mead and L. Conway (eds.), Addison-Wesley, 1980, Sect. 8.3.

    Google Scholar 

  14. H. T. Kung et al., “The Warp Computer: Architecture, Implementation, and Performance”, IEEE Trans. on Computers C-36, 12 (Dec. 1987), 1523–1538.

    Google Scholar 

  15. M. Lam, “A Systolic Array Optimizing Compiler”, Ph. D. Thesis, Department of Computer Science, Carnegie-Mellon University, May 1987.

    Google Scholar 

  16. P. Lee, Z. Kedem, “Synthesizing Linear Array Algorithms from Nested for Loop Algorithms”, Tech. Report 355, Department of Computer Science, Courant Institute of Mathematical Sciences, New York University, Mar. 1988

    Google Scholar 

  17. C. Lengauer, “A Methodology for Programming with Concurrency: The Formalism”, Science of Computer Programming 2, 1 (Oct. 1982), 19–52.

    Google Scholar 

  18. C. Lengauer, “On the Projection Problem in Systolic Design”, Tech. Report CMU-CS-88-102, Computer Science Department, Carnegie-Mellon University, Feb. 1988.

    Google Scholar 

  19. C. Lengauer and J. Sanders, “The Projection of Systolic Programs”, Proc. Conference on Mathematics of Program Construction, June 1989, to appear as Springer-Verlag Lecture Notes of Computer Science.

    Google Scholar 

  20. P. J. Lieu, Personal communication, Department of Computer Science, Carnegie-Mellon University, Nov. 1987.

    Google Scholar 

  21. J. R. McGraw et al., “SISAL Language Reference Manual, Version 1.2”, Manual M-146, Lawrence Livermore National Laboratory, University of California at Davis, Mar. 1985.

    Google Scholar 

  22. D. I. Moldovan and J. A. B. Fortes, “Partitioning and Mapping Algorithms into Fixed-Size Systolic Arrays”, IEEE Trans. on Computers C-35, 1 (Jan. 1986), 1–12.

    Google Scholar 

  23. D.I. Moldovan, “ADVIS: A Software Package for the Design of Systolic Arrays”, IEEE Trans. on Computer-Aided Design CAD-6, 1 (Jan. 1987), 33–40.

    Google Scholar 

  24. P. Quinton, “The Systematic Design of Systolic Arrays”, Tech. Report 193, Publication Interne IRISA, Apr. 1983; also: TR84-11, The Microelectronics Center of North Carolina, May 1984.

    Google Scholar 

  25. P. Quinton et al., “Designing Systolic Arrays with DIASTOL”, in VLSI Signal Processing II, S.-Y. Kung, R. E. Owen, and J. G. Nash (eds.), IEEE Press, 1986, 93–105.

    Google Scholar 

  26. P. Quinton et al., “Synthesizing Systolic Arrays Using DIASTOL”, in Systolic Arrays, W. Moore, A. McCabe, and R. Urquart (eds.), Adam Hilger, 1987, 25–36.

    Google Scholar 

  27. P. Quinton, “Mapping Recurrences on Parallel Architectures”, in Supercomputing '88 (ICS 88), Vol. III: Supercomputer Design: Hardware & Software, L. P. Kartashev and S. I. Kartashev (eds.), Int. Supercomputing Institute, Inc., 1988, 1–8.

    Google Scholar 

  28. S. K. Rao, “Regular Iterative Algorithms and their Implementations on Processor Arrays”, Ph. D. Thesis, Department of Electrical Engineering, Stanford University, Oct. 1985.

    Google Scholar 

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Eddy Odijk Martin Rem Jean-Claude Syre

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© 1989 Springer-Verlag Berlin Heidelberg

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Lengauer, C. (1989). Towards systolizing compilation: An overview. In: Odijk, E., Rem, M., Syre, JC. (eds) PARLE '89 Parallel Architectures and Languages Europe. PARLE 1989. Lecture Notes in Computer Science, vol 366. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-51285-3_45

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  • DOI: https://doi.org/10.1007/3-540-51285-3_45

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