Skip to main content

An example of integrated circuit design based on silicon compilation: The SCPC1 (Silicon Compiler Pyramidal Chip)

  • Algorithms And Techniques
  • Chapter
  • First Online:
Recent Issues in Pattern Analysis and Recognition

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 399))

Abstract

The paper describes a new chip for image processing, the SCPC1 (Silicon Compiler Pyramidal Chip) as an example of application of a very innovative CAD tool: a silicon compiler. The new chip is the result of a restructuring of a typical pyramidal architecture previously realized in a more conventional way (see Section I.) The restructuring aim is the creation of a more flexible and modular system exploiting the most important capabilities of a silicon compiler, described in Section II. Section III deals with some relevant problems and solutions related to the application of silicon compilation to ASIC, taking as example the realization of SCPC1.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

V. References

  1. V. Cantoni, S. Levialdi, G. Musso: Image Analysis and Processing. Plenum Press, New York, 1986.

    Google Scholar 

  2. P.E. Danielsson, S. Levialdi: Computer Architectures for Pictorial Information Systems. “IEEE Computer”, vol. 14, n. 11, 1981, p. 53–68.

    Google Scholar 

  3. M.J.B. Duff: Clip4: A large Scale Integrated Circuit Array Parallel Processor. "3rd International Joint Conference on Pattern Recognition" 1976 p. 728–732.

    Google Scholar 

  4. A. P. Reeves: A Systematically Designed Binary Array Processor. "IEEE Trans. on Computers" vol. C-29, No. 4, 1980, p. 278–287.

    Google Scholar 

  5. K. Preston: Cellular Logic Computers for Pattern Recognition. "IEEE Computer" vol.15, No. 1, 1983, p. 36–47.

    Google Scholar 

  6. V. Cantoni: Classification Schemes for Image Processing Architecture. "NATO ASI on Computer Architecture for Spatially Distributed Data" Cetraro, 1983.

    Google Scholar 

  7. R. W. Hockney, C.R. Jessope: Parallel Computers. Adam Higler Ldt, Bristol, 1981.

    Google Scholar 

  8. L. Uhr: Pyramid Multicomputer Structures and Augmented Pyramids. In: M. J. B. Duff, Ed. Computing Structures for Image processing, Academic Press, London, 1983, p. 95–112.

    Google Scholar 

  9. V. Cantoni, M. Ferretti, S. Levialdi, R. Stefanelli: Papia: Pyramidal Architecture for Parallel Image Analysis. "IEEE Proc. of 7th Simposium on Computer Arithmetic" June 4–6, 1985, Urbana, IL.

    Google Scholar 

  10. K. E. Batcher: Design of a Massively Parallel Processor. "IEEE Trans. on Computers" vol. C-29, No. 9, 1980, p. 836–840.

    Google Scholar 

  11. Daniel D. Gajski: Silicon Compilation. Addison-Wesley, 1987.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Virginio Cantoni Reiner Creutzburg Stefano Levialdi G. Wolf

Rights and permissions

Reprints and permissions

Copyright information

© 1989 Springer-Verlag Berlin Heidelberg

About this chapter

Cite this chapter

Albanesi, M.G. (1989). An example of integrated circuit design based on silicon compilation: The SCPC1 (Silicon Compiler Pyramidal Chip). In: Cantoni, V., Creutzburg, R., Levialdi, S., Wolf, G. (eds) Recent Issues in Pattern Analysis and Recognition. Lecture Notes in Computer Science, vol 399. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-51815-0_46

Download citation

  • DOI: https://doi.org/10.1007/3-540-51815-0_46

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-51815-0

  • Online ISBN: 978-3-540-46815-8

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics