Abstract
A puzzle whose solution has applications in VLSI layout compaction of memories and fine grained parallel processors can be phrased as follows:
You are given a set of n rectangles arranged in a coordinate plane such that no two overlap and each rectangle has sides parallel to the coordinate axes. The width of such an arrangement is the length of a longest horizontal line segment having each of its endpoints located within the rectangles. You may slide the rectangles only in the direction of the horizontal axis and may not slide any rectangle over another. Find a minimal width arrangement reachable by sliding from the original arrangement.
The fastest previously known algorithm solving this problem is the iterative approach of Mehlhorn and RĂ¼lling [6] requiring O(n 2 log n) time. This paper develops and proves correct a simple O(n log n) time algorithm which exploits the geometric structure of the constraints between the rectangles.
This research was supported by NSF Presidential Young Investigator Grant MIP-8657693
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
P. Eichenberger and M. Horowitz, Toroidal Compaction of Symbolic Layouts for Regular Structures, 1987 ICCAD, pp. 142–145.
Z. Galil and E. Tardos, An O(n 2(m + n log n) log n) Min-Cost Flow Algorithm, 1986 FOCS, pp. 1–9.
G. Kedem and H. Watanabe, Graph-Optimization Techniques for IC layout and Compaction, 1983 DAC, pp. 113–120.
T. Lengauer, The Complexity of Compacting Hierachically Specified Layouts of Integrated Circuits, 1982 FOCS, pp. 358–368.
Y.Z. Liao and C. K. Wong, An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints, IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. CAD-2, No.2, 1983.
K. Mehlhorn and W. RĂ¼lling, Compaction on the Torus, 1988 AWOC, pp 212–225.
T. Ohtsuki, gen. ed., Layout Design and Verification, Elsevier Science Pub. B.V. (North Holland), 1986, Chapter 6: Layout Compaction, D. Mlynski and C-H. Sung.
M. Schlag, Y. Z. Liao, and C. K. Wong, An Algorithm for Optimal Two-Dimensional Compaction of VLSI Layouts, Research Report RC 9739, IBM T. J. Watson Research Center, 1982.
R. E. Tarjan, Personal communication, 1988.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1990 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Anderson, R., Kahan, S., Schlag, M. (1990). An O(n log n) algorithm for 1-D tile compaction. In: Nagl, M. (eds) Graph-Theoretic Concepts in Computer Science. WG 1989. Lecture Notes in Computer Science, vol 411. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-52292-1_21
Download citation
DOI: https://doi.org/10.1007/3-540-52292-1_21
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-52292-8
Online ISBN: 978-3-540-46950-6
eBook Packages: Springer Book Archive