Abstract
A parallel hardware accelerator for the speed-up of massively parallel processing systems is discussed. Its architecture is based on multi-functional combinational networks distributed over many processors and interconnected by sets of open collector lines. This accelerator allows to compute logical vector functions, based on searching, comparison, and sorting operations, and parallel exchange of data. Each processor is able to determine the correct result of an operation by taking into account its local characteristics only and those specified for the whole system. To achieve this result we introduce a new method which minimizes the processing time. The method is based on proving necessary and sufficient conditions, which allow to form all possible sets of individual time delays for processors involved in the parallel logical operation. The results shown allow to speed up the hardware realization of massively logical operations in multiple bus parallel processors. They can also be used for designing specialized high performance systems, e.g. schemes for finding maximum or minimum values, the median, or for implementing different priority schemes.
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© 1990 Springer-Verlag Berlin Heidelberg
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Makhaniok, M., Chemiavsky, V., Männer, R., Stucky, O. (1990). Massively parallel realization of logical operations in distributed parallel systems. In: Burkhart, H. (eds) CONPAR 90 — VAPP IV. VAPP CONPAR 1990 1990. Lecture Notes in Computer Science, vol 457. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-53065-7_155
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DOI: https://doi.org/10.1007/3-540-53065-7_155
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