Abstract
A new evaluation model for SK combinator expressions is presented and used as a basis for the design of a novel processor. The resulting machine architecture resembles a dataflow ring, but executions are constrained to be fully lazy. When used in a multiprocessor context, different grains of parallelism are exploited at different architectural levels. A dynamic load sharing mechanism based on the current physical state of the machine is suggested. Initial simulation results are presented, and the cost-effectiveness of the proposed architecture is discussed.
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© 1991 Springer-Verlag
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Waite, M., Giddings, B., Lavington, S. (1991). Parallel associative combinator evaluation. In: Aarts, E.H.L., van Leeuwen, J., Rem, M. (eds) PARLE '91 Parallel Architectures and Languages Europe. PARLE 1991. Lecture Notes in Computer Science, vol 506. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-54152-7_74
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DOI: https://doi.org/10.1007/3-540-54152-7_74
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