Effective implementation of distributed arbitration in multiprocessor systems

Abstract

Distributed arbitration schemes as implemented, e.g., in Futurebus and MultibusII, use a fixed arbitration time for the acquisition procedure defining new bus mastership. This time corresponds to the maximum settling delay required by a decentralized combinational logic of the arbitration scheme and depends on the set of all possible arbitration numbers which are assigned to processors requesting the bus. In this paper, a new method for reducing bus acquisition time is described which exploits the dependency of the delay time required on the arbitration numbers. The theorem that defines this dependency is derived. The application of the proposed method allows to reduce the delay time in each module and therefore the whole time of the arbitration process considerably. It is shown, that the average bus acquisition time can be shortened, e.g., by 30%. The proposed method is directly suitable for improving the performance of standard multiprocessor buses.