Abstract
This paper presents a data flow architecture that utilizes task level parallelism by the architectural structure of a distributed memory multiprocessor, instruction level parallelism by a token-passing computation scheme, and subinstruction level parallelism by SIMD evaluation of complex machine instructions. Sequential threads of data instructions are compiled to data flow macro actors and executed consecutively using registers.
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© 1992 Springer-Verlag Berlin Heidelberg
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Ungerer, T., Zehendner, E. (1992). Threads and subinstruction level parallelism in a data flow architecture. In: Bougé, L., Cosnard, M., Robert, Y., Trystram, D. (eds) Parallel Processing: CONPAR 92—VAPP V. VAPP CONPAR 1992 1992. Lecture Notes in Computer Science, vol 634. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-55895-0_476
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DOI: https://doi.org/10.1007/3-540-55895-0_476
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