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Analysis of the TMS320C40 communication channels using timed Petri Nets

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Application and Theory of Petri Nets 1993 (ICATPN 1993)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 691))

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Abstract

The Texas Instruments' TMS320C40 Digital Signal Processor's communication ports and their associated DMA channels have been modelled using Timed Petri Nets. The Petri Net implementation is discussed, and the performance of the communication ports/DMA channels are evaluated. Analysis of the simulation results indicate that the single DMA bus provides insufficient bandwidth to drive the communication ports at maximum speed. During split mode operation the requirement to exchange the bus token reduces the communication bandwidth.

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References

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  3. Texas Instruments Inc., TMS320C4x User's Guide, 1991.

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  4. Dally, W.J. and Song, P., “Design of a Self-Timed VLSI Multicomputer Communication Controller”, Proc. International Conference on Computer Design, pp. 230–234, 1987.

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  5. Marsan, M.A., “Stochastic Petri Nets: An Elementary Introduction”, Advances in Petri Nets, G. Rozenberg (ed), Springer-Verlag, pp. 1–29, 1989.

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Authors and Affiliations

  1. Coherent and Electro-Optics Research Group, Liverpool John Moores University, Byrom Street, L3 3AF, Liverpool, UK

    David A. Hartley & David M. Harvey

Authors
  1. David A. Hartley
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  2. David M. Harvey
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Marco Ajmone Marsan

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© 1993 Springer-Verlag Berlin Heidelberg

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Hartley, D.A., Harvey, D.M. (1993). Analysis of the TMS320C40 communication channels using timed Petri Nets. In: Ajmone Marsan, M. (eds) Application and Theory of Petri Nets 1993. ICATPN 1993. Lecture Notes in Computer Science, vol 691. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-56863-8_68

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  • DOI: https://doi.org/10.1007/3-540-56863-8_68

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-56863-6

  • Online ISBN: 978-3-540-47759-4

  • eBook Packages: Springer Book Archive

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