Automatic one-hot re-encoding for FPGAs

Abstract

The most common design migrated from PLDs to FPGAs is a state machine. Because of the wide input gates available in PLDs, fully encoded state machines are usually used. However, in register rich FPGAs with narrower gates, one-hot state machines are usually preferred. This paper describes a logic synthesis algorithm which automatically translates a functional level encoded state machine to an equivalent one-hot machine. The result is that without any manual redesign, a PLD state machine can be optimally re-implemented in an FPGA technology such as Xilinx or Actel.