Abstract
The most common design migrated from PLDs to FPGAs is a state machine. Because of the wide input gates available in PLDs, fully encoded state machines are usually used. However, in register rich FPGAs with narrower gates, one-hot state machines are usually preferred. This paper describes a logic synthesis algorithm which automatically translates a functional level encoded state machine to an equivalent one-hot machine. The result is that without any manual redesign, a PLD state machine can be optimally re-implemented in an FPGA technology such as Xilinx or Actel.
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References
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Brayton, R. K, G. D. Hachtel, C. T. McMullen and A. L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, Kluver Academic Publishers, 1985
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© 1993 Springer-Verlag Berlin Heidelberg
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Allen, D. (1993). Automatic one-hot re-encoding for FPGAs. In: Grünbacher, H., Hartenstein, R.W. (eds) Field-Programmable Gate Arrays: Architecture and Tools for Rapid Prototyping. FPL 1992. Lecture Notes in Computer Science, vol 705. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-57091-8_31
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DOI: https://doi.org/10.1007/3-540-57091-8_31
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Online ISBN: 978-3-540-47902-4
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