Abstract
The new family of Field Programmable Gate Arrays, CLI6000 from Concurrent Logic Inc realizes the truly Cellular Logic. It has been mainly designed for the realization of data path architectures. However, introduced by it new universal logic cell calls also for new logic synthesis methods based on regularity of connections. In this paper we present two programs, exact and approximate, for the minimization of Permuted Reed-Muller Trees that are obtained by repetitive application of Davio expansions (Shannon expansions for EXOR gates) in all possible orders of variables in subtrees. Such trees are particularly well matched to both the realization of logic cell and connection structure of the CLI6000 device. It is shown on several standard benchmarks that the heuristic algorithm gives good quality results in much less time than the exact algorithm.
This research was partially supported by the NSP grant MIP-9110772
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© 1993 Springer-Verlag Berlin Heidelberg
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Wu, LF., Perkowski, M.A. (1993). Minimization of permuted Reed-Muller Trees for cellular logic programmable Gate arrays. In: Grünbacher, H., Hartenstein, R.W. (eds) Field-Programmable Gate Arrays: Architecture and Tools for Rapid Prototyping. FPL 1992. Lecture Notes in Computer Science, vol 705. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-57091-8_32
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DOI: https://doi.org/10.1007/3-540-57091-8_32
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