Abstract
This paper presents a design methodology to support the design of embedded information processing units in mechatronic systems during early design phases. System partitioning into a set of software and hardware modules is done at system description level. User guided and automated synthesis tools generate a fully functional prototype that can be connected to the mechanical subsystem to estimate system performance. The spectrum of realizations ranges from single task software implementations on a single standard processor to application specific integrated processors in a heterogeneous multi-processor environment. In this paper emphasis is put on high level synthesis aspects for the ASIP emulation part of the whole system.
This research was sponsored by the DFG through SFB 241 ’IMES’and ESPRIT BRA 3281
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
S. Walters, Computer Aided Prototyping for ASIC-based Systems, IEEE Design and Test of Computers, June 1991
P. Poechmueller, M. Glesner, HADES-High Level Architecture Development and Exploration System First Great Lake Symposium on VLSI, Kalamazoo, Michigan, pp. 342–343, March 1991
F. Catthoor, N. Wehn, P. Poechmueller, et al, Novel ASIC Architecture and Synthesis Methodologies for Future Multiplexed Datapath Designs, CompEuro91, Bologna, pp. 506–511, May 1991
L. Stok, R. van den Born, EASY: Multiprocessor Architecture Optimisation, Logic and Architecture Synthesis for Silicon Compilers, pp.313–327, North-Holland, 1990
A. Laudenbach, M. Glesner, G. Hohenberg, E. Nitzschke, D. Koehler, Real Time Heat Release Calculation of Combustion Engines, Proceedings of 24th ISATA International Symposium on Automotive Technology and Automation, Florence, May 20–24, pp.733–740, 1991
J. Rabaey, M. Potkonjak, Retiming for Scheduling, VLSI Signal Processing IV, IEEE Press, pp. 23–32, 199
G. Goosens, J. Vandewalle, H. De Man, Loop optimization in register transfer scheduling for DSP-systems, Proceedings of 26th Design Automation Conference, pp. 826–831, Las Vegas, 1989
C.E. Leiserson, F.M. Rose, Optimizing Synchronous Circuitry by Retiming, Third Caltech Conference on Very Large Scale Integration, Computer Science Press, 1983
N. Wehn, M. Held, M. Glesner, A Novel Scheduling/Allocation Approach for Datapath Synthesis based on Genetic Paradigms, Logic and Architecture Synthesis, pp. 47–56, published by North-Holland, 1991
H.-J. Herpel, N. Wehn, M. Glesner, RAMSES — A Rapid Prototyping Environment for Embedded Control Applications, Proceedings Second Int. Workshop on Rapid System Prototyping, Research Triangle Park, June 1991
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1993 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Poechmueller, P., Herpel, H.J., Glesner, M., Longsen, F. (1993). High level synthesis in an FPGA-based computer aided prototyping environment. In: Grünbacher, H., Hartenstein, R.W. (eds) Field-Programmable Gate Arrays: Architecture and Tools for Rapid Prototyping. FPL 1992. Lecture Notes in Computer Science, vol 705. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-57091-8_34
Download citation
DOI: https://doi.org/10.1007/3-540-57091-8_34
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-57091-2
Online ISBN: 978-3-540-47902-4
eBook Packages: Springer Book Archive