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High level synthesis in an FPGA-based computer aided prototyping environment

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Field-Programmable Gate Arrays: Architecture and Tools for Rapid Prototyping (FPL 1992)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 705))

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Abstract

This paper presents a design methodology to support the design of embedded information processing units in mechatronic systems during early design phases. System partitioning into a set of software and hardware modules is done at system description level. User guided and automated synthesis tools generate a fully functional prototype that can be connected to the mechanical subsystem to estimate system performance. The spectrum of realizations ranges from single task software implementations on a single standard processor to application specific integrated processors in a heterogeneous multi-processor environment. In this paper emphasis is put on high level synthesis aspects for the ASIP emulation part of the whole system.

This research was sponsored by the DFG through SFB 241 ’IMES’and ESPRIT BRA 3281

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Herbert Grünbacher Reiner W. Hartenstein

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© 1993 Springer-Verlag Berlin Heidelberg

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Poechmueller, P., Herpel, H.J., Glesner, M., Longsen, F. (1993). High level synthesis in an FPGA-based computer aided prototyping environment. In: Grünbacher, H., Hartenstein, R.W. (eds) Field-Programmable Gate Arrays: Architecture and Tools for Rapid Prototyping. FPL 1992. Lecture Notes in Computer Science, vol 705. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-57091-8_34

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  • DOI: https://doi.org/10.1007/3-540-57091-8_34

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-57091-2

  • Online ISBN: 978-3-540-47902-4

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