Abstract
This paper describes a new approach to synthesize a costefficient self-test hardware for a given set of deterministic test patterns. To minimize the test hardware effort, instead of all the patterns only a very small subset has to be selected such that an easy generation of all necessary test patterns is ensured. This procedure drastically decreases the storage requirements (over 80%) and therefore reduces distinctly the selftest hardware effort. The realization of an external self-test by a specific test chip was done with XILINX FPGAs, since field-programmable gatearrays are best-suited for applications with a low production volume. Experimental results on all the ISCAS benchmark circuits underline the efficiency of our approach.
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© 1993 Springer-Verlag Berlin Heidelberg
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Kunzmann, A. (1993). FPGA based self-test with deterministic test patterns. In: Grünbacher, H., Hartenstein, R.W. (eds) Field-Programmable Gate Arrays: Architecture and Tools for Rapid Prototyping. FPL 1992. Lecture Notes in Computer Science, vol 705. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-57091-8_42
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DOI: https://doi.org/10.1007/3-540-57091-8_42
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