On reconfigurability of VLSI linear arrays

Abstract

Fault tolerance through the incorporation of redundancy and reconfiguration is quite common. In a redundant linear array of processing elements, k redundant links of fixed lengths are provided to each element of the array in addition to the regular links connecting neighboring processors. The redundant links may be activated to bypass faulty elements. The number and the distribution of faults can have severe impact on the effectiveness of such a method. In this paper we study the problem of deciding whether a pattern of n blocks of faults is catastrophic for a redundant array. We prove that, for arrays provided of bidirectional links, the problem requires time O(kn). In the unidirectional case we propose an algorithm whose complexity is O(n) when the array has only one redundant link, and O(kn log k) otherwise. When the pattern is not catastrophic we are interested to obtain a reconfiguration set and, in particular, an optimal reconfiguration set (i.e. one with maximal number of working elements). We prove that such a problem is NP-hard, when the links are bidirectional. For the unidirectional case, instead, we present an algorithm of complexity O(kng), where g is the length of the longest link.