Abstract
In this paper a methodology for verifying RISC cores is presented. This methodology is based on a hierarchical model of interpreters. This model allows us to define formal specifications at each level of abstraction and successively prove the correctness between the neighbouring abstraction levels, so that the overall specification is correct with respect to its hardware implementation. The correctness proofs have been split into two steps so that the parallelism in the execution due to the pipelining of instructions, is accounted for. The first step shows that the instructions are correctly processed by the pipeline and the second step shows that the semantic of each instruction is correct. We have implemented the specification of the entire model and performed parts of the proofs in HOL.
This work has been partly financed by a german national grant, project Automated System Design, SFB No.358.
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Cohn, A.: A Proof of the Viper Microprocessor The First Level; In: VLSI Specification, Verification and Synthesis, Eds. G. Birtwistle and P.A. Subrahmanyam, Kluwer, 1988.
Hennessy, J., Patterson, D.: Computer Architecture A Quantitative Approach; Morgan Kaufmann Publishers, Inc. San Mateo, California, 1990.
Hunt, W.: The Mechanical Verification of a Microprocessor Design; In: From HDL Description to Guaranteed Correct Circuit Designs, Ed. D. Borrione, North-Holland, 1987.
Joyce, J.: Multi-Level Verification of Microprocessor-Based Systems; PhD thesis, Cambridge University, December 1989.
Kumar, R., Schneider, K., Kropf, Th.: Structuring and Automating Hardware Proofs in a Higher-Order Theorem-Proving Environment; Journal of Formal Methods in System Design, Vol. 2, pp. 165–230, 1993.
Melham, Th.:Abstraction Mechanisms for Hardware Verification; In: VLSI Specification, Verification and Synthesis, Eds. G. Birtwistle and P. A. Subrahmanyam, Kluwer, 1988.
Srivas, M., Bickford, M.: Verification of a Pipelined Microprocessor Using Clio; In: Hardware Specification, Verification and Synthesis: Mathematical Aspects, Eds. M. Leeser and G. Brown, Springer, 1990.
Tahar, S., Kumar, R.: A Formalization of a Hierarchical Model for RISC Processors; to appear in Proc. of Euro-ARCH'93, Munich, Germany, Springer Verlag, 1993.
Tahar, S., Kumar, R.: Towards a Methodology for the Formal Hierarchical Verification of RISC Processors; to appear in Proc. of the 1993 International Conference on Computer Design, Cambridge, Massachusetts, IEEE, 1993.
Windley, P.: The Formal Verification of Generic Interpreters; PhD thesis, University of California, Davis, Division of Computer Science, July 1990.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1994 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Tahar, S., Kumar, R. (1994). Implementing a methodology for formally verifying RISC processors in HOL. In: Joyce, J.J., Seger, CJ.H. (eds) Higher Order Logic Theorem Proving and Its Applications. HUG 1993. Lecture Notes in Computer Science, vol 780. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-57826-9_142
Download citation
DOI: https://doi.org/10.1007/3-540-57826-9_142
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-57826-0
Online ISBN: 978-3-540-48346-5
eBook Packages: Springer Book Archive