Skip to main content

Dependence-conscious global register allocation

  • Session Papers
  • Conference paper
  • First Online:
Programming Languages and System Architectures

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 782))

Abstract

Register allocation and instruction scheduling are antagonistic optimizations: Whichever is applied first, it will impede the other. To solve this problem, we propose dependence-conscious colouring, a register allocation method that takes the dependence graph used by the instruction scheduler into consideration. Dependence-conscious colouring consists of two parts: First, the interference graph is built by analysing the dependence graphs, resulting in fewer interference edges and less spilling than the conventional preordering approach. Second, during colouring the register selection keeps dependence paths short, ensuring good scheduling. Dependence-conscious colouring reduces the number of interference edges by 7%–24% and antidependences by 46%–100%.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Marc Auslander and Martin Hopkins. An overview of the PL.8 compiler. In SIGPLAN '82 [SIG82], pages 22–31.

    Google Scholar 

  2. Preston Briggs, Keith D. Cooper, Ken Kennedy, and Linda Torczon. Coloring heuristics for register allocation. In SIGPLAN '89 Conference on Programming Language Design and Implementation, pages 275–284, 1989.

    Google Scholar 

  3. David G. Bradlee, Susan J. Eggers, and Robert R. Henry. Integrating register allocation and instruction scheduling for RISCs. In Architectural Support for Programming Languages and Operating Systems (ASPLOS-IV), pages 122–131, 1991.

    Google Scholar 

  4. Paul Beusterien. Personal communication, 1992.

    Google Scholar 

  5. Preston Briggs. Personal communication, 1992.

    Google Scholar 

  6. Preston Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, Houston, 1992.

    Google Scholar 

  7. Gregory J. Chaitin, Marc A. Auslander, Ashok K. Chandra, John Cocke, Martin E. Hopkins, and Peter W. Markstein. Register allocation via coloring. Computer Languages, 6(1):45–57, 1981. Reprinted in [Sta90].

    Google Scholar 

  8. Fred C. Chow and John L. Hennessy. The priority-based coloring approach to register allocation. ACM Transactions on Programming Languages and Systems, 12(4):501–536, October 1990.

    Google Scholar 

  9. G. J. Chaitin. Register allocation & spilling via graph coloring. In SIGPLAN '82 [SIG82], pages 98–105.

    Google Scholar 

  10. Stefan M. Freudenberger and John C. Ruttenberg. Phase ordering of register allocation and instruction scheduling. In Robert Giegerich and Susan L. Graham, editors, Code Generation — Concepts, Tools, Techniques, Workshops in Computing, pages 146–170. Springer, 1991.

    Google Scholar 

  11. James R. Goodman and Wei-Chung Hsu. Code scheduling and register allocation in large basic blocks. In International Conference on Supercomputing, pages 442–452, 1988.

    Google Scholar 

  12. Phillip B. Gibbons and Steve S. Muchnick. Efficient instruction scheduling for a pipelined architecture. In SIGPLAN '86 Symposium on Compiler Construction, pages 11–16, 1986.

    Google Scholar 

  13. John Hennessy and Thomas Gross. Postpass code optimization of pipeline constraints. ACM Transactions on Programming Languages and Systems, 5(3):422–448, July 1983.

    Google Scholar 

  14. W. G. Morris. CCG: A prototype coagulating code generator. In SIGPLAN '91 [SIG91], pages 45–58.

    Google Scholar 

  15. Todd A. Proebsting and Charles N. Fischer. Linear-time, optimal code scheduling for delayed-load architectures. In SIGPLAN '91 [SIG91], pages 256–267.

    Google Scholar 

  16. Shlomit S. Pinter. Register allocation with instruction scheduling: A new approach. In SIGPLAN '93 Conference on Programming Language Design and Implementation, pages 248–257, 1993. SIGPLAN Notices 28(6).

    Google Scholar 

  17. B. R. Rau, M. Lee, P. P. Tirumalai, and M. S. Schlansker. Register allocation for software pipelined loops. In SIGPLAN '92 Conference on Programming Language Design and Implementation, pages 283–299, 1992.

    Google Scholar 

  18. SIGPLAN '82 Symposium on Compiler Construction, 1982.

    Google Scholar 

  19. SIGPLAN '91 Conference on Programming Language Design and Implementation, 1991.

    Google Scholar 

  20. William Stallings, editor. Reduced Instruction Set Computers. IEEE Computer Society Press, second edition, 1990.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Jürg Gutknecht

Rights and permissions

Reprints and permissions

Copyright information

© 1994 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Ambrosch, W., Ertl, M.A., Beer, F., Krall, A. (1994). Dependence-conscious global register allocation. In: Gutknecht, J. (eds) Programming Languages and System Architectures. Lecture Notes in Computer Science, vol 782. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-57840-4_28

Download citation

  • DOI: https://doi.org/10.1007/3-540-57840-4_28

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-57840-6

  • Online ISBN: 978-3-540-48356-4

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics