A scalable bit-sequential SIMD architecture for pattern recognition

Abstract

A scalable SIMD architecture has been developed for the most efficient implementation of binary pattern classification by nearestneighbor algorithms. A two-dimensional M × N array of asynchronous counters, reflecting an inherent two-fold data parallelism of the applications, reduces the data transfer to off-chip memory from $\mathcal{O}(M \times N)$ to $\mathcal{O}(M + N)$ which allows a high integration and efficient use of external memory. Here, we present the realization of a VLSI structure, the system architecture, and possible applications including binary kNN and a completely binary version of k-means.