Exploiting locality in LT-RAM computations

Abstract

As processor speeds continue to increase the primary assumption of the RAM model, that all memory locations may be accessed in unit time, becomes unrealistic. In the following we consider an alternative model, called the Limiting Technology or LT-RAM, where the cost of accessing a given memory location is dependent on the size of the memory module. In general, computations which are performed on an LT-RAM with a memory of size n × n will result in execution times which are n times slower than a comparable RAM, if no special precautions are taken. Here we provide a general technique by which, for a class of algorithms, this slow-down can be reduced to O(2^{6·log 1/2 n}) for sequential memory access, or to just O(1) if the memory access can be pipelined.

This research was partially supported by the Leonardo Fibonacci Institute for the Foundations of Computer Science, and by EC Cooperative Action IC-1000 (project ALTEC: Algorithms for Future Technologies).