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On Steiner minimal trees in grid graphs and its application to VLSI routing

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Algorithms and Computation (ISAAC 1994)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 834))

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Abstract

In this paper we present an algorithm for Steiner minimal trees in grid graphs with all terminals located on the boundary of the graph. The algorithm runs in O(k 2*mink 2 log k, n) time, where k and n are the numbers of terminals and vertices of the graph, respectively. It can handle non-convex boundaries and is the fastest known for this case. We also describe a new approach to the homotopic routing problem in VLSI layout design, which applies our Steiner tree algorithm to construct minimum-length wires for multi-terminal nets.

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Author information

Authors and Affiliations

  1. Wilhelm-Schickard-Institut für Informatik, Universität Tübigen, Sand 13, 72076, Tübingen, Germany

    Michael Kaufmann

  2. Department of Electronic and Computer Engineering, Concordia University, 1455 De Maisonneuve Blvd. West, H3G 1M8, Montreal, Canada

    Shaodi Gao & K. Thulasiraman

Authors
  1. Michael Kaufmann
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  2. Shaodi Gao
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  3. K. Thulasiraman
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Editor information

Ding-Zhu Du Xiang-Sun Zhang

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© 1994 Springer-Verlag Berlin Heidelberg

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Kaufmann, M., Gao, S., Thulasiraman, K. (1994). On Steiner minimal trees in grid graphs and its application to VLSI routing. In: Du, DZ., Zhang, XS. (eds) Algorithms and Computation. ISAAC 1994. Lecture Notes in Computer Science, vol 834. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58325-4_199

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  • DOI: https://doi.org/10.1007/3-540-58325-4_199

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-58325-7

  • Online ISBN: 978-3-540-48653-4

  • eBook Packages: Springer Book Archive

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