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Influence of logic block layout architecture on FPGA performance

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Field-Programmable Logic Architectures, Synthesis and Applications (FPL 1994)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 849))

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Abstract

Among the several FPGA technologgies available today, the comparison of tiiming performances is always device dependent.In order to compare accurately the performances of the logic block architectures used in FPGA's families, we have implemented different functions.Using a layout synthesizer we evaluate post layout performances of these functions.A methodology to optimize the size of transistor gates in Look-up Tables is proposed

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References

  1. S. Singh, J. Rose, P. Chow, D. Lewis ”The effect of logic Block architecture on FPGA performance”IEEE Journal of Solid State Circuits, Vol. 27, N∘3, March 1992.

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Authors and Affiliations

  1. Sciences-LIRMM, UMR 9928 CNRS/UMII, Universite Montpellier II, 161 rue Ada (case 477), 34392, Montpellier cedex 5, France

    M. Robert, L. Torres, F. Moraes & D. Auvergne

Authors
  1. M. Robert
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  2. L. Torres
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  3. F. Moraes
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  4. D. Auvergne
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Reiner W. Hartenstein Michal Z. Servít

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© 1994 Springer-Verlag Berlin Heidelberg

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Robert, M., Torres, L., Moraes, F., Auvergne, D. (1994). Influence of logic block layout architecture on FPGA performance. In: Hartenstein, R.W., Servít, M.Z. (eds) Field-Programmable Logic Architectures, Synthesis and Applications. FPL 1994. Lecture Notes in Computer Science, vol 849. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58419-6_67

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  • DOI: https://doi.org/10.1007/3-540-58419-6_67

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-58419-3

  • Online ISBN: 978-3-540-48783-8

  • eBook Packages: Springer Book Archive

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