Abstract
An algorithm for formal verification of the set of timing rules that express timing discipline in digital systems is described. It is based on a digital system specification model and notation transferrable to VHDL and concerns formal consistency verification at the design level of system specification development procedure.
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References
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© 1994 Springer-Verlag Berlin Heidelberg
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Bartos, T., Fristacky, N. (1994). Formal verification of timing rules in design specifications. In: Hartenstein, R.W., ServÃt, M.Z. (eds) Field-Programmable Logic Architectures, Synthesis and Applications. FPL 1994. Lecture Notes in Computer Science, vol 849. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58419-6_76
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DOI: https://doi.org/10.1007/3-540-58419-6_76
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