Abstract
A new approach based on using alternative graphs (AG) to create tools for computer aided test pattern design for digital systems is proposed. Different representation levels of digital systems (behavioral, procedural, functional, logical and topological ones) are supported by uniform test design tools based on the same AG-formalism. Instead of using different libraries of component models for solving different test design tasks (fault analysis, test synthesis, multivalued simulation, testability analysis), only a single library of AGs will be used, which reduces the cost of creating and updating component libraries. Aoverview of the model and methods is given and a description of a system for automated test program generation is described.
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Abadir M.S., Reghbati H.K. Functional specification and testing of logic circuits. Comp. I Math. with Appls. Vol. 11, No.12, pp. 1143–1153., 1985.
Abramovici M., Breuer M.A. Multiple fault diagnosis in combinational circuits based on an effect-cause analysis. IEEE Trans. Comp., vol. C-29, June, 1980, pp. 451–460.
Akers S.B. 1978). Binary decision diagrams. IEEE Trans. on Computers, Vol. 27, pp. 509–516.
Anirudhan P.N., Menon P.R. Symbolic test generation for hierarchically modeled digital systems. 1989 International Test Conference, pp.461–469.
Beenker F.P.M. et al. Macro testing: Unifying IC and board test. IEEE Design and test of computers. Dec. 1986, pp.26–32.
Calhoun J.D., Brglez F. A framework and method for hierarchical test generation. IEEE International Test Conference, 1989, pp.480–490.
Chandra S.J., Patel J.H. A hierarchical approach to test vector generation. ACM/IEEE 24th Design Automation Conf., June 1987, pp.495–501.
Cheng K.-T., Jou J.-Y. Functional test generation for finite state machines. IEEE International Test Conference, 1990, pp.162–168.
Ghosh A., Chakraborty T.J. On behavior fault modeling for digital designs. J. of Electronic Testing. Theory and Applications, 2, 135–151 (1991).
Giambiasi N. et. al. Test pattern generation for behavioral descriptions in VHDL. Proc. of the VHDL conference, Stockholm, 1991, pp.228–234.
Gupta A.G., Armstrong J.R. Functional fault modeling and simulation for VLSI devices. ACM/IEEE 22nd DAC, 1985, pp.720–726.
Kobayashi K. Functional test data generation for hardware design verification. 1987 IEEE International Test Conferation, pp.547–552.
Krishnamurthy B. Hierarchical test generation: Can AI help? IEEE International Test Conference, Sept. 1987, pp.694–700.
Kuchcinski K. Towards automatic test pattern generation for VHDL description. Proc. of the VHDL conference, Stockholm. 1991.
Kunda R.P., Abraham J.A., Rathi B.D. Speedup of test generation using high-level primitive. ACM/IEEE 27th DAC, pp.580–586, June 1990.
Lee J., Patel J.H. An architectural level test generator for a hierarchical design environment. 21th Int.Symp. on FTC, June, 1991, pp.44–51.
Leenstra J., Spaanenburg L. Hierarchical test assembly for macro based VLSI design. 1990 International Test Conference, pp.520–529.
Lin T., Su S.Y.H. VLSI functional test pattern generation — a design and implementation. 1985 International Test Conference, pp.922–929.
Murray B.T., Hayes J.P. Hierarchical test generation using precomputed tests for modules. IEEE 1988 International Test Conference. pp.221–229.
Murray B.T., Hayes J.P. Test propagation through modules and circuits. 1991 International Test Conference, pp.748–757.
Sarfert T.M., Markgraf R., Trischler E., Schulz M.H. Hierarchical test generation based on high-level primitives. IEEE 1989 ITC, pp.470–479.
Saucier G., Bellon C. CADOC: A system for computer aided functional test. IEEE 1984 International Test Conference, pp.680–687.
Saucier G., Crastes de Paulet M., Tiar F. Functional test of ASICs and Boards. F.Lombardi and M.Sami (eds.). Testing and Diagnosis of VLSI and ULSI. 273–286. 1988 by Kluwer Academic Publishers.
Shen L., Su S.Y.H. A functional testing method for microprocessors. IEEE Trans. on Computers, Oct. 1988, pp. 1288–1293.
Su S.Y.H., Lin T. (1984). Functional testing techniques for digital LSI/VLSI systems. ACM/IEEE 21st DAC, 1984, pp.517–528.
Thatte S.M., Abraham I.A. (1980). Test generation for microprocessors. IEEE Trans. on Computers, Vol. 29. pp. 429–441.
Ubar R. Test generation for digital circuits using alternative graphs. Proc. of Tallinn Technical University, Estonia, No.409, pp.75–81 (in Russian).
Ubar R. Vektorielle alternative Graphen und Fehlerdiagnose für digitale Systeme. Nachrichtentechnik/Elektronik (Germany) 31(1981) H.I. s. 25–28.
Ubar R. Test pattern generation for digital systems on the vector AG-model. 13th Int.Conf.on Fault Tolerant Computing, Milano,Italy,1983, pp.347–351.
Ubar R. Alternative graphs and technical diagnosis of digital devices. Electronic technique. (USSR) Vol.8. No.5 (132). pp.33–57 (in Russian).
Ubar R., Dushina J., Zaugarow S., Krupnova L., Storozhew S. (1993). FTGEN — A system for functional test generation. Proc. of the Int. Conf. CAD 93. Yalta, May 4–13. 1993, pp. 123–125.
Ward P.C., Armstrong J.R. (1990). Behavioral fault simulation in VHDL ACM/IEEE 27th Design Automation Conference, 1990, pp.587–593.
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© 1994 Springer-Verlag Berlin Heidelberg
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Ubar, R. (1994). Test generation for digital systems based on alternative graphs. In: Echtle, K., Hammer, D., Powell, D. (eds) Dependable Computing — EDCC-1. EDCC 1994. Lecture Notes in Computer Science, vol 852. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58426-9_129
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DOI: https://doi.org/10.1007/3-540-58426-9_129
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