Abstract
A unified classification of delay fault tests that covers all representative types of tests for path and gate delay faults is presented. Timing-related definitions of delay fault testability are transformed into conditions that do not involve circuit delays. These conditions are subsequently used to develop a procedure for fast, simulation-free grading of delay faults. It is shown that, depending on what “detection of a delay fault by an input pattern” means, a randomly generated test sequence can provide very different values of fault coverage; these values range, for one of the examined benchmark circuits, from 13% to over 99%.
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S. Devadas, K. Keutzer, “Synthesis of Robust Delay-Fault-Testable Circuits: Theory,” IEEE Trans. Computer-Aided Design, vol. 11, pp. 87–101, Jan. 1992.
K. Fuchs, H. C. Wittmann, K. J. Antreich, “Fast Test Pattern Generation for All Path Delay Faults Considering Various Test Classes,” Proc. European Test Conf., pp. 89–98, 1993.
C. T. Glover, M. R. Mercer, “A Method of Delay Fault Test Generation,” Proc. 25th Design Automation Conf., pp. 90–95, 1988.
V. S. Iyengar, B. K. Rosen, J. A. Waicukauski, “On Computing the Sizes of Detected Delay Faults,” IEEE Trans. Computer-Aided Design, vol. 9, pp. 299–312, March 1990.
B. Könemann et al., “Delay Test: The Next Frontier for LSSD Test Systems,” Proc. Int. Test Conf., pp. 578–587, 1992.
A. KraŚniewski, L. B. Wroński, “Testability of Delay Faults,” Tech. Report, Warsaw Univ. of Technology, Institute of Telecommunications, Jan. 1994.
C. J. Lin, S. M. Reddy, “On Delay Fault Testing in Logic Circuits,” IEEE Trans. Computer-Aided Design, vol. 6, pp. 694–703, Sept. 1987.
W. Mao, M. D. Ciletti, “A Quantitative Measure for Robustness for Delay Fault Testing,” Proc. European Design Automation Conf., pp. 543–549, 1992.
P. C. Maxwell, “Let's Grade ALL the Faults,” Proc. Int. Test Conf., pp. 595, 1993.
E. S. Park, M. R. Mercer, “Robust and Nonrobust Tests for Path Delay Faults in a Combinational Circuit,” Proc. Int. Test Conf., pp. 1027–1034, 1987.
E. S. Park, M. R. Mercer, “An Efficient Delay Test Generation System for Combinational Logic Circuits,” IEEE Trans. Computer-Aided Design, vol. 11, pp. 926–938, July 1992.
A. K. Pramanick, S. M. Reddy, “On the Detection of Delay Faults,” Proc. Int. Test Conf., pp. 845–856, 1988.
A. K. Pramanick, S. M. Reddy, “On the Design of Path Delay Fault Testable Combinational Circuits,” Proc. 20th Fault Tolerant Computing Symp., pp. 374–381, 1990.
E. S. Park, B. Underwood, T. W. Williams, M. R. Mercer, “Delay Testing in Timing-Optimized Designs,” Proc. Int. Test Conf., pp. 897–905, 1991.
J. Savir, W. H. McAnney, “Random Pattern Testability of Delay Faults,” IEEE Trans. Computers, vol. 37, pp. 291–300, March 1988.
K. D. Wagner, C. K. Chin, E. J. McCluskey, “Pseudorandom Testing”, IEEE Trans. on Computers, vol. 36, pp. 332–343, Mar. 1987.
J. A. Waicukauski, E. Lindbloom, B. K. Rosen, V. S. Iyengar, “Transition Fault Simulation,” IEEE Design & Test of Computers, pp. 32–38, April 1987.
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© 1994 Springer-Verlag Berlin Heidelberg
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KraŚniewski, A., Wroński, L.B. (1994). Coverage of delay faults: When 13% and 99% mean the same. In: Echtle, K., Hammer, D., Powell, D. (eds) Dependable Computing — EDCC-1. EDCC 1994. Lecture Notes in Computer Science, vol 852. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58426-9_131
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DOI: https://doi.org/10.1007/3-540-58426-9_131
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