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Coverage of delay faults: When 13% and 99% mean the same

  • Session 4: Hardware testing
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Dependable Computing — EDCC-1 (EDCC 1994)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 852))

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Abstract

A unified classification of delay fault tests that covers all representative types of tests for path and gate delay faults is presented. Timing-related definitions of delay fault testability are transformed into conditions that do not involve circuit delays. These conditions are subsequently used to develop a procedure for fast, simulation-free grading of delay faults. It is shown that, depending on what “detection of a delay fault by an input pattern” means, a randomly generated test sequence can provide very different values of fault coverage; these values range, for one of the examined benchmark circuits, from 13% to over 99%.

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Klaus Echtle Dieter Hammer David Powell

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© 1994 Springer-Verlag Berlin Heidelberg

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KraŚniewski, A., Wroński, L.B. (1994). Coverage of delay faults: When 13% and 99% mean the same. In: Echtle, K., Hammer, D., Powell, D. (eds) Dependable Computing — EDCC-1. EDCC 1994. Lecture Notes in Computer Science, vol 852. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58426-9_131

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  • DOI: https://doi.org/10.1007/3-540-58426-9_131

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-58426-1

  • Online ISBN: 978-3-540-48785-2

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