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Detection of permanent hardware faults of a floating point adder by pseudoduplication

  • Session 8: Software diversity
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Dependable Computing — EDCC-1 (EDCC 1994)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 852))

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Abstract

In this paper the detection of hardware faults by pseudoduplication for a special floating point adder is investigated. For a special floating point adder all single stuck-at-0/1 faults are injected. In a first simulation experiment for random input patterns all the faults are determined which can be detected by pseudoduplication. In a second experiment for sequences of random input vectors with different lenght the probability to detect an arbitrary single fault is determined.

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References

  1. Assaad, F.T., Dutt, S.: “More Robust Test in Algorithm-Based Fault-TolerantMatrix Multiplication”, Proc. FTCS-22, pp430–439, 1992

    Google Scholar 

  2. Cavanagh, J.: “Digital Computer Arithmetic”, Mc Graw-Hill, 1984

    Google Scholar 

  3. Echtle, K., Hinz, B., Nikolov, T.: “On hardware fault detection by diverse software”, Fault Tolerant Systems & Diagnostics (FTSD-13), Varna, 1990, pp 362–367

    Google Scholar 

  4. Goldberg, D.: “What every computer scientist should know about floating-point arithmetic”, ACM Computing Surveys, Vol. 23, No.1, March 1991, pp5–45

    Google Scholar 

  5. Hahn,W.and Gössel,M.:“Pseudoduplication of Floating Point Faults”, Proc. 1991 IEEE VLSI Test Symposium, Atlantic City,April 15–17, ppl61–165.

    Google Scholar 

  6. IEEE Standard for Binary Floating-Point Arithmetic ANSI/IEEE Std 754-1985, New York, August 1985

    Google Scholar 

  7. Laha, S., Patel, J., H.: “Error Correction in Arithmetic Operations. Using Time Redundancy”, 13th Int. Symp. Fault Tolerant Comp., Milano, 1984, ppl98–205

    Google Scholar 

  8. Minero, R. H., Anello, A. J., Furey, R. G., Palounek, L. R.: “Checking by pseudoduplication”, US PS 3660646, GO6F 11/00,1972

    Google Scholar 

  9. Patel, J. H., Fung, L. Y.: “Concurrent Error Detection in Multiply and Divide Arrays”, IEEE Trans. Comp. C-32 (1983), pp417–422

    Google Scholar 

  10. Sparmann,U.:“Strukturbasierte Testmethode fuer arithm. Schaltkreise”, Dissertation,Saarbruecken, 1991

    Google Scholar 

  11. Wei, D.D, Kim, J. H., Rao, T. R. N.: “CompleteTests in Algorithm-Based Fault-Tolerant Matrix Operationson Processor Arrays”, Proc. IEEE Int. Workshop Defect and Fault Tolerance in VLSI Systems, pp255–262, Venice 1993.

    Google Scholar 

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Klaus Echtle Dieter Hammer David Powell

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© 1994 Springer-Verlag Berlin Heidelberg

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Gerber, S., Goessel, M. (1994). Detection of permanent hardware faults of a floating point adder by pseudoduplication. In: Echtle, K., Hammer, D., Powell, D. (eds) Dependable Computing — EDCC-1. EDCC 1994. Lecture Notes in Computer Science, vol 852. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58426-9_139

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  • DOI: https://doi.org/10.1007/3-540-58426-9_139

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-58426-1

  • Online ISBN: 978-3-540-48785-2

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