Skip to main content
SpringerLink
Log in

Feasible regions quantify the configuration power of arrays with multiple fault types

  • Session 10: Fault tolerance in VLSI
  • Conference paper
  • First Online:
Dependable Computing — EDCC-1 (EDCC 1994)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 852))

Included in the following conference series:

Abstract

The bulk of closed-form results for the performance of configuration architectures are of a univariate nature. The corresponding analyses treat the case of failed processors, but neglect broken interconnect and switches. The present paper considers the combined effects of all of these fault types. We show how solutions to this multivariate problem can be expressed as feasible regions of fault tolerance. Optimum solutions can be computed by known methods in linear or nonlinear programming. For the sake of illustration we characterize the worst-case behavior of a simple but practical means of organizing redundancy: local sparing.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Douglas M. Blough. “On the Reconfiguration of Memory Arrays Containing Clustered Faults”. Proceedings, 21st International Symposium on Fault Tolerant Computing. pp 444–451.

    Google Scholar 

  2. [Chapman et al 1994] G.H. Chapman, L. Carr, M.J. Syrzycki, and B. Dufort, “Test Vehicle for a Wafer-Scale Thermal Pixel Scence Simulator”. In Proceedings, International Conference on Wafer Scale Integration. R. M. Lea and Stuart Tewksbury, eds. IEEE Computer Society. San Francisco. January, 1994. pp 1–10.

    Google Scholar 

  3. [Chapman et al 1992] G.H. Chapman, M. Parameswaran, and M.J. Syrzycki, “Wafer Scale Transducer Arrays”. IEEE Computer, special issue on Wafer Scale Integration. Vol 25. 4. 1992. pp 50–56.

    Google Scholar 

  4. [Czechowski et al 1989] J. Czechowski, E. H. Rogers, and M-J Chung. “Architectural Yield Analysis of Random Defects in Wafer Scale Integration”. In Proceedings, International Conference on Wafer Scale Integration. Earl Swartzlander and Joe Brewer, eds. IEEE Computer Society. San Francisco. January. 1989. pp 215–244.

    Google Scholar 

  5. J. P. Hayes. “A Graph Model for Fault Tolerant Computing Systems”, IEEE Transactions on Computers. Vol C-25, September, 1976. pp 875–884.

    Google Scholar 

  6. Ajai Jain and Janusz Rajski. “Probabilistic Analysis of Yield and Area Utilization”. In Proceedings, International Workshop on Defect and Fault Tolerance in VLSI Systems. IEEE Computer Society. October. 1988. pp 7.1.1–12.

    Google Scholar 

  7. Israel Koren and Dhiraj K. Pradhan. “Yield and Performance Enhancement in VLSI and WSI Multiprocessor Systems”. Proceedings of the IEEE. Vol 74, No 5, May, 1986. pp 699–711.

    Google Scholar 

  8. S. Y. Kuo and W. K. Fuchs. “Efficient Spare Allocation for Reconfigurable Arrays”. IEEE Design and Test. February. 1987. pp 24–31.

    Google Scholar 

  9. Laurence E. LaForge. “Extremally Fault Tolerant Arrays”. Proceedings, International Conference on Wafer Scale Integration. Earl Swartzlander and Joe Brewer, eds. San Francisco: IEEE Computer Society, January, 1989.

    Google Scholar 

  10. Laurence E. LaForge. Fault Tolerant Arrays. PhD dissertation. Montreal: McGill University, 1991.

    Google Scholar 

  11. Laurence E. LaForge. “What Designers of Wafer Scale Systems Should Know About Local Sparing”. Proceedings, IEEE International Conference on Wafer Scale Integration. R. M. Lea and Stuart Tewksbury, eds. San Francisco: IEEE Computer Society. January, 1994.

    Google Scholar 

  12. Tom Leighton and Charles E. Leiserson. “Wafer-scale Integration of Systolic Arrays”, IEEE Transactions on Computers. Vol C-34, No 5. May, 1985. pp 448–461.

    Google Scholar 

  13. F. Preparata, G. Metze, and R. Chien. “On the Connection Assignment Problem of Diagnosable Systems”. IEEE Transactions on Computers. EC-16, 1967. pp 848–854.

    Google Scholar 

  14. W. Shi and W. K. Fuchs. “Probabilistic Analysis of Reconfiguration Heuristics”. Proceedings, International Workshop on Defect and Fault Tolerance in VLSI Systems. New York: Plenum Press. 1989.

    Google Scholar 

  15. P. Turán. “On the Theory of Graphs”. Colloquium Mathematicum. Vol III, 1954. pp 19–30.

    Google Scholar 

  16. Kuochen Wang and Jenn-Wei Lin. “Integrated Diagnosis and Reconfiguration Process for Defect Tolerant WSI Processor Arrays”. In Proceedings, International Conference on Wafer Scale Integration. R. Mike Lea and Stuart Tewksbury, eds. IEEE Computer Society. San Francisco. January, 1994. pp 198–207.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electrical Engineering, MS 260 University of Nevada, 89557-0153, Reno, NV

    Laurence E. LaForge

Authors
  1. Laurence E. LaForge
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Klaus Echtle Dieter Hammer David Powell

Rights and permissions

Reprints and permissions

Copyright information

© 1994 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

LaForge, L.E. (1994). Feasible regions quantify the configuration power of arrays with multiple fault types. In: Echtle, K., Hammer, D., Powell, D. (eds) Dependable Computing — EDCC-1. EDCC 1994. Lecture Notes in Computer Science, vol 852. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58426-9_152

Download citation

  • DOI: https://doi.org/10.1007/3-540-58426-9_152

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-58426-1

  • Online ISBN: 978-3-540-48785-2

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation