Abstract
Verifying abstract operations, such as bus transactions, is a hard problem that is not well served by existing theorem proving methods. This problem has aspects in common with the familiar model checking problem of verifying temporal logic formulas against a state machine implementation. The contribution of this paper is a new approach to efficiently handle such proofs for circuits that are built using standard library components. The fundamental idea is to prove and then store away temporal properties for the individual components of the library. Our initial results show that this approach can result in an order of magnitude execution speedup for circuit proofs that use these components. This is combined with a drastic reduction in the level of user interaction needed to construct the proofs. This work provides a promising direction for future research into effective proof automation.
This research was partially funded by NASA-Langley Research Center under contract NAS1-18586, Task 10. The NASA technical monitor was Sally Johnson.
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D. Fura, P. Windley, and G. Cohen, “Formal Design Specification of a Processor Interface Unit,” NASA Contractor Report 189698, November 1992.
D.A. Fura, P.J.Windley, and A.K. Somani, “Abstraction Techniques for Modeling Real-World Interface Chips,” in J. Joyce and C. Seger (eds.), Higher-Order Logic Theorem Proving and its Applications, Lecture Notes in Computer Science 780, Springer-Verlag, 1994.
D. Fura, P. Windley, and G. Cohen, “Towards the Formal Specification of a Processor Interface Unit,” NASA Contractor Report 4521, December 1993.
D. Fura, P. Windley, and G. Cohen, “Towards the Formal Verification of a Processor Interface Unit,” NASA Contractor Report 4522, December 1993.
D.A. Fura, Abstract Interpreter Modeling and Verification Methods for Embedded Hardware and Fault-Tolerant Systems, Ph.D. thesis, Electrical Engineering Department, University of Washington, 1994.
M.J.C. Gordon and T.F. Melham, Introduction to HOL: A Theorem Proving Environment for Higher Order Logic, Cambridge University Press, 1993.
F.K. Hanna and N. Daeche, “Specification and Verification using Higher-Order Logic: A Case Study,” in G.J. Milne and P.A. Subrahmanyam (eds.), Formal Aspects of VLSI Design, Elsevier Science Publishers, 1986, pp. 179–213.
J. Herbert, “Formal Verification of Basic Memory Devices,” Technical Report No. 124, Computer Laboratory, University of Cambridge, February 1988.
H. Hungar, “Combining Model Checking and Theorem Proving to Verify Parallel Processes,” in C. Courcoubetis (ed.), Fifth Conference on Computer Aided Verification, Lecture Notes in Computer Science 697, Springer-Verlag, 1993, pp. 154–165.
Intel Corporation, 80960MC Hardware Designer's Reference Manual, June 1989.
J.J. Joyce and C.H. Seger, “Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving,” in Proceedings of the 30th Design Automation Conference, IEEE Computer Society Press, June 1993.
R.P. Kurshan and L. Lamport, “Verification of a Multiplier: 64 Bits and Beyond,” in C. Courcoubetis (ed.), Fifth Conference on Computer Aided Verification, Lecture Notes in Computer Science 697, Springer-Verlag, 1993, pp. 166–179.
B. Moszkowski, “A Temporal Logic for Multilevel Reasoning about Hardware,” IEEE Computer, Vol. 18, No. 2, February 1985, pp. 10–19.
T.F. Melham, Formalizing Abstraction Mechanisms for Hardware Verification in Higher Order Logic, Ph.D. thesis and Technical Report No. 201, Computer Laboratory, University of Cambridge, August 1990.
K. Schneider, R. Kumar, and T. Kropf, “Alternative Proof Procedures for Finite-State Machines in Higher-Order Logic,” in J. Joyce and C. Seger (eds.), 1993 International Workshop on Higher Order Logic Theorem Proving and its Applications, Vancouver, Canada, August 1993, pp. 215–228.
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© 1994 Springer-Verlag Berlin Heidelberg
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Fura, D.A., Somani, A.K. (1994). Interval-semantic component models and the efficient verification of transaction-level circuit behavior. In: Melham, T.F., Camilleri, J. (eds) Higher Order Logic Theorem Proving and Its Applications. HUG 1994. Lecture Notes in Computer Science, vol 859. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58450-1_44
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DOI: https://doi.org/10.1007/3-540-58450-1_44
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