Abstract
An important verification problem for concurrent systems in general is that of establishing whether one system is a correct implementation, or refinement, of another system. For untimed systems, trace inclusion (or variants such as failure inclusion) is often used as a criterion of refinement. The natural extension of this criterion to timed systems is timed trace-inclusion. Unfortunately, this problem is undecidable for the commonly used model of timed automata (i.e. finite-state automata extended with clocks) due to the expressive power of the model. This is a serious obstacle to the application of automatic verification methods to timed automata. In this paper, we show that the problem of timed trace-inclusion is decidable for a large and natural class of processes in Reed and Roscoe's Timed CSP [RR86]. Essentially, this class includes static networks of processes with finite-control structure and real-valued clocks (modelled implicitly by a delay operator).
This work is supported by the Swedish Board for Industrial and Technical Development (NUTEK) and the Swedish Research Council for Engineering Sciences (TFR).
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Yi, W., Jonsson, B. (1994). Decidability of timed language-inclusion for networks of real-time communicating sequential processes. In: Thiagarajan, P.S. (eds) Foundation of Software Technology and Theoretical Computer Science. FSTTCS 1994. Lecture Notes in Computer Science, vol 880. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58715-2_129
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DOI: https://doi.org/10.1007/3-540-58715-2_129
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