Skip to main content
SpringerLink
Log in

New trends in simulation of distributed shared memory architectures

  • Conference paper
  • First Online:
Parallel Computing Technologies (PaCT 1995)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 964))

Included in the following conference series:

  • 122 Accesses

Abstract

In this paper we review several issues related to simulation of modern distributed shared memory architectures: workload selection and characterization, processor-memory interaction, memory simulation and simulation efficiency. These issues are discussed in the context of several modern architecture simulation workbenches. Various efficient simulation techniques are presented. In particular, we discuss the feasibility of parallel discrete event simulation techniques and argue that this is a promising approach for efficient simulation of parallel computer architectures.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. L. Barriga and R. Ayani. Parallel Cache Simulation on Multiprocessor Workstations. In Proceedings of the International Conference in Parallel Processing, Illinois, Aug. 1993.

    Google Scholar 

  2. L. Barrozo, S. Iman, J. Jeong, K. Öner, K. Ramamurthy, and M. Dubois. RPM: A Rapid Prototyping Engine for Multiprocessor Systems. IEEE Computer, pages 26–34, Feb. 1995.

    Google Scholar 

  3. R. Bedichek. Some Efficient Architecture Simulation Techniques. In Proceedings of the Winter USENIX Conference, pages 53–63, January 1990.

    Google Scholar 

  4. E. Brewer, C. Dellarocas, A. Colbrook, and W. E. Weihl. PROTEUS: A High Performance Parallel-Architecture Simulator. Technical Report MIT/LCS/TR-516, Laboratory for Computer Science, Massachusetts Institute of Technology, September 1991.

    Google Scholar 

  5. M. Brorsson, F. Dahlgren, H. Nilsson, and P. Stenström. The CacheMire Test Bench — A Flexible and Effective Approach for Simulation of Multiprocessors. In Proceedings of the 26th Annual Simulation Symposium, pages 41–49, March 1993.

    Google Scholar 

  6. B. Cmelik and D. Keppel. Shade: A Fast Instruction-Set Simulator for Execution Profiling. In Proceedings of the ACM Sigmetrics Conf. on Measurement & Modeling of Computer Systems, pages 128–137, May 1994.

    Google Scholar 

  7. R. Covington, S. Dwarkadas, J. Jump, S. Madala, and J. Sinclair. Efficient Simulation of Computer Systems. International Journal in Computer Simulation, 1(1):31–58, June 1991.

    Google Scholar 

  8. H. Davis, S. Goldschmidt, and J. Hennessy. Multiprocessor Simulation and Tracing Using Tango. In Proceedings of the International Conference on Parallel Processing, pages II99–II107, August 1991.

    Google Scholar 

  9. R. M. Fujimoto. Parallel discrete event simulation. Communications of the ACM, 33(10):30–53, October 1990.

    Google Scholar 

  10. R. Goldschmidt and J. Hennessy. The Accuracy of Trace-Driven Simulations of Multiprocessors. In Proceedings of the ACM Sigmetrics Conf. on Measurement & Modeling of Computer Systems, volume 21(1), pages 146–157, May 1993.

    Google Scholar 

  11. J. Heinlein, K. Gharachorloo, S. Dresser, and A. Gupta. Integration of Message Passing and Shared Memory in the Stanford FLASH Multiprocessor. In Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 38–50, October 1994.

    Google Scholar 

  12. S. Herrod, E. Witchel, M. Rosenblum, and A. Gupta. Fast and Accurate Multiprocessor Simulation: The SimOS Approach. To appear in IEEE Parallel and Distributed Technology, Fall 1995.

    Google Scholar 

  13. D. R. Jefferson. Virtual time. ACM Transactions on Programming Languages and Systems, 7(3):404–425, July 1985.

    Google Scholar 

  14. D. Kranz, K. Johnson, A. Agarwal, J. Kubiatowicz, and B.-H. Lim. Integrating Message-Passing and Shared-Memory: Early Experience. In Proceedings of the 4th Symposium on Principles and Practices of Parallel Programming, pages 54–63, May 1993.

    Google Scholar 

  15. Y.-B. Lin, J.-L. Baer, and E. Lazowska. Tailoring a Parallel Trace-Driven Simulation Technique to Specific Multiprocessor Cache Coherence Protocols. In Proceedings of the SCS Multiconference on Distributed Simulation, pages 185–190, March 1989.

    Google Scholar 

  16. P. Magnusson. A Design for Efficient Simulation of a Multiprocessor. In Proceedings of the Int. Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), pages 69–78, January 1993.

    Google Scholar 

  17. P. Magnusson. Efficient Memory Simulation in SimICS. In Proceedings of the 28th Annual Simulation Symposium, March 1995.

    Google Scholar 

  18. A. M. G. Maynard, C. M. Donelly, and B. R. Olszewski. Contrasting Characteristics and Cache Performance of Technical and Multi-User Commercial Workloads. In Proceedings of the Sixth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 145–156, October 1994.

    Google Scholar 

  19. J. Misra. Distributed-discrete event simulation. ACM Computing Surveys, 18(1):39–65, March 1986.

    Google Scholar 

  20. H. Muller, P. Stallard, D. Warren, and S. Raina. Parallel Evaluation of a Parallel Architecture by Means of Calibrated Emulation. In Proceedings of the 8th International Parallel Processing Symposium, pages 260–267, April 1994.

    Google Scholar 

  21. S. K. Reinhardt, M. D. Hill et.al. The Wisconsin Wind Tunnel: Virtual Prototyping of Parallel Computers. In Proceedings of the ACM Sigmetrics Conf. on Measurement & Modeling of Computer Systems, volume 21, pages 48–60, May 1993.

    Google Scholar 

  22. J. P. Singh, J. Hennesy, and A. Gupta. Scaling Parallel Programs for Multiprocessors: Methodology and Examples. IEEE Computer, 26(7):42–50, July 1993.

    Google Scholar 

  23. J. P. Singh, W.-D. Weber, and A. Gupta. SPLASH: Stanford Parallel Applications for Shared-Memory. Computer Architecture News, 20(1):5–44, March 1993.

    Google Scholar 

  24. D. Thiebaut, J. Wolf, and H. Stone. Synthetic Traces for Trace-Driven Simulation of Cache Memories. IEEE Transactions on Computers, pages 388–410, April 1992.

    Google Scholar 

  25. R. Uhlig, D. Nagle, T. Mudge, and S. Sechrest. Kernel-based Memory Simulation. In Proceedings of the ACM Sigmetrics Conference on Measurement & Modeling of Computer Systems, volume 22(1), pages 286–287, May 1994.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Dept. of Teleinformatics, Royal Institute of Technology, S-16440, Kista, Sweden

    Luis Barriga & Rassul Ayani

Authors
  1. Luis Barriga
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Rassul Ayani
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Victor Malyshkin

Rights and permissions

Reprints and permissions

Copyright information

© 1995 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Barriga, L., Ayani, R. (1995). New trends in simulation of distributed shared memory architectures. In: Malyshkin, V. (eds) Parallel Computing Technologies. PaCT 1995. Lecture Notes in Computer Science, vol 964. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-60222-4_121

Download citation

  • DOI: https://doi.org/10.1007/3-540-60222-4_121

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-60222-4

  • Online ISBN: 978-3-540-44754-2

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation