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FPGA implementation of a rational adder

  • Arithmetic and Signal Processing
  • Conference paper
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Field-Programmable Logic and Applications (FPL 1995)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 975))

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Abstract

A systolic coprocessor for the addition of signed normalized rational numbers is implemented using field programmable logic from Atmel. The circuit is structured as a sandwich of systolic arrays implementing the necessary subtasks: integer GCD, exact division, multiplication and addition/subtraction. In particular, the implementation of GCD and of exact division improve significantly (2 to 4 times) previously known solutions. In contrast to the traditional approach, all operations are performed least-significant digits first, which allows bit-pipelining between partial operations at reduced area-cost. The actual implementation for 8-bit operands consumes 730 cells (3,500 equivalent gates) and runs at 25 MHz (5 MHz after layout).

Supported by Austrian FWF grant P10002-PHY.

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Authors and Affiliations

  1. RISC-Linz, A-4040, Linz, Austria

    Tudor Jebelean

Authors
  1. Tudor Jebelean
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Editor information

Will Moore Wayne Luk

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© 1995 Springer-Verlag Berlin Heidelberg

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Jebelean, T. (1995). FPGA implementation of a rational adder. In: Moore, W., Luk, W. (eds) Field-Programmable Logic and Applications. FPL 1995. Lecture Notes in Computer Science, vol 975. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-60294-1_119

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  • DOI: https://doi.org/10.1007/3-540-60294-1_119

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-60294-1

  • Online ISBN: 978-3-540-44786-3

  • eBook Packages: Springer Book Archive

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