Abstract
Recently, there has been a renewal of interest in self-timed systems, due to their modularity, robustness, low-power consumption and average-case performance. Additionally, this paper argues that there are specific benefits to adopting self-timed design for FPGAs. The mapping problems of placement, routing and partitioning are simplified by not having a global clock constraint to meet, so more mappings are available for mapping algorithms to choose from. Hence, there is greater potential for algorithms to improve utilisation and performance of a design, or instead, to increase design turn-around by taking less time to produce a mapping. Furthermore, the ability to perform mappings quickly enables new FPGA applications where the mapping to the FPGA is done on-the-fly. However, currently available FPGAs provide no support for self-timed design. The latter half of the paper describes the STACC architecture, an FPGA architecture targeted at the implementation of self-timed bundled-data systems.
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© 1995 Springer-Verlag Berlin Heidelberg
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Payne, R. (1995). Self-timed FPGA systems. In: Moore, W., Luk, W. (eds) Field-Programmable Logic and Applications. FPL 1995. Lecture Notes in Computer Science, vol 975. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-60294-1_95
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DOI: https://doi.org/10.1007/3-540-60294-1_95
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