Abstract
This paper introduces a general scheme for formally embedding high level synthesis by formulating its basic steps as transformations within higher order logic. A functional representation of a data flow graph is successively refined by means of generic logical transformations. Algorithms that are based on logical transformations guarantee “correctness by design”. They not only construct an implementation but also derive the proof for its formal correctness, on the fly. An extra postsynthesis-verification step becomes obsolete. The logical transformations presented in this paper form a framework for formally embedding existing high-level-synthesis procedures.
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Eisenbiegler, D., Kumar, R. (1995). Formally embedding existing high level synthesis algorithms. In: Camurati, P.E., Eveking, H. (eds) Correct Hardware Design and Verification Methods. CHARME 1995. Lecture Notes in Computer Science, vol 987. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-60385-9_5
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DOI: https://doi.org/10.1007/3-540-60385-9_5
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