Abstract
Asynchronous Transfer Mode (ATM) switches are the basic components of Broadband Integrated Services Digital Networks (B-ISDN). A wide variety of architectures have been proposed. The quantitative performance evaluation of ATM exchanges (and networks) under real world operating conditions is a (very) challenging problem due to the high cell throughput, the scalable size, and complex architectures. In this work, it is shown that parallel processing, with an implementation on an MIMD machine, allows us to make very detailed simulation experiments on a real world exchange of non-trivial size (up to 2048X2048 155Mbit/s links). Implementation strategies and actual run-times are presented. An analytic model of the simulator performance provides a quantitative tool for the optimization of the price/performance of this class of problems on a wide variety of current and future parallel and distributed machine architectures.
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References
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© 1996 Springer-Verlag Berlin Heidelberg
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Liu, W., Petit, G., Dirkx, E. (1996). Simulation of ATM exchanges on a parallel computer. In: Liddell, H., Colbrook, A., Hertzberger, B., Sloot, P. (eds) High-Performance Computing and Networking. HPCN-Europe 1996. Lecture Notes in Computer Science, vol 1067. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61142-8_650
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DOI: https://doi.org/10.1007/3-540-61142-8_650
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