Abstract
The multiplication operation and the computation of symmetric functions are fundamental problems in arithmetic and algebraic computation. We describe unit-weight threshold circuits to perform the multiplication of two n-bit integers, which have fan-in k, edge complexity O(n 2+1/d), and depth O(log d + log n/log k), for any fixed integer d > 0. For a given fan-in, our constructions have considerably smaller depth (or edge complexity) than the beat previous circuits of similar edge complexity (or depth, respectively). Similar results are also shown for the iterated addition operation and the computation of symmetric functions. In particular, we propose a unit-weight threshold circuit to compute the sum of m n-bit numbers that has fan-in k, edge complexity O(nm 1+1/d), and depth O(log d + log m/log k + log n/log k).
Research supported partially by NSF under grant NSF-RIA-08930554.
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© 1996 Springer-Verlag Berlin Heidelberg
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Yeh, CH., Varvarigos, E.A. (1996). Depth-efficient threshold circuits for multiplication and symmetric function computation. In: Cai, JY., Wong, C.K. (eds) Computing and Combinatorics. COCOON 1996. Lecture Notes in Computer Science, vol 1090. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61332-3_156
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DOI: https://doi.org/10.1007/3-540-61332-3_156
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