Abstract
This paper presents the VPN tool (VHDL to Petri Nets) for translating a subset of VHDL'87 into a formal model based on Interpreted and Timed Petri Nets (ITPN). This formal model finds its application to different kind of analysis such as symbolic model checking, behavioral equivalence and behavioral synthesis of the VHDL descriptions.
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© 1996 Springer-Verlag Berlin Heidelberg
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Bawa, R.K., Encrenaz, E. (1996). A tool for translation of VHDL descriptions into a formal model and its application to formal verification and synthesis. In: Jonsson, B., Parrow, J. (eds) Formal Techniques in Real-Time and Fault-Tolerant Systems. FTRTFT 1996. Lecture Notes in Computer Science, vol 1135. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61648-9_59
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DOI: https://doi.org/10.1007/3-540-61648-9_59
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